M30245 Ver la hoja de datos (PDF) - Renesas Electronics
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M30245 Datasheet PDF : 266 Pages
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M30245 Group
Description
Table 1.3 Pin description
Port
Function
Power supply input
CPU mode switch
Pin Name
Vcc
Vss
CNVss
External data bus width select BYTE
input
Reset input
Clock input
Clock output
RESET
XIN
XOUT
Analog power supply input
Reference voltage input
Low pass filter
USB power supply input
Vbus detect
USB D+
USB D-
P0 I/O port
AVcc
AVss
VREF
LPF
UVcc
VbusDTCT
USB D+
USB D-
P00 to P07
Data bus
AND Flash control
P1 I/O port
Data bus
AND Flash control
P2 I/O port
Address bus
P3 I/O port
Address bus
P4 I/O port
Address bus
Chip select
P5 I/O port
Bus control
D0 to D7
AND_DATA0 to 7
P10 to P17
D8 to D15
AND_SC
AND_WE
AND_OE
P20 to P27
A0 to A 7
P30 to P37
A8 to A 15
P40 to P47
A16 to A 19
CS0 to CS3
P50 to P57
WRL/WR
WRH/BHE
RD
BCLK
HOLD
HLDA
ALE
RDY
I/O
Description
3.0 to 3.6V
0V
I Connect to Vss: single-chip or memory expansion mode
Connect to Vcc: Microprocessor mode only
I Selects external memory data bus width.
Connect to Vss: 16-bit.
Connect to Vcc: 8-bit.
I "L" resets the microcomputer.
I These pins support the main clock generating circuit. Connect a crystal between
O the XIN and XOUT pins. To use an external clock, input it to the XIN pin and leave
the XOUT pin open.
Connect to Vcc.
Connect to Vss.
I This is a reference voltage for A/D converter.
O Loop filter for the frequency synthesizer circuit.
Power pin for USB
I Detects USB host power
I/O USB D+ voltage line interface
I/O USB D- voltage line interface
I/O This is an 8-bit CMOS I/O port. The input/output port direction register allows
each pin to be set individually. When used for input, the port can be set to
include internal pull-up resistors in 4-pin blocks.
I/O These pins input and output 8 low-order data bits when set as a separate bus.
I/O Data pins for communicating with AND type flash memory devices
I/O This is an 8-bit I/O port equivalent to P0.
I/O These pins input and output 8 high-order data bits when set as a separate bus.
O Control signal pins for communicating with AND type flash memory devices
I/O This is an 8-bit I/O port equivalent to P0.
O These pins output 8 low-order address bits.
I/O This is an 8-bit I/O port equivalent to P0.
O These pins output 8 middle-order address bits.
I/O This is an 8-bit I/O port equivalent to P0.
O These pins output 4 high-order address bits.
O P44 to P47 are chip select output pins that specify access areas.
I/O This is an 8-bit I/O port equivalent to P0.
O Ouput WRL, WRH (WR, BHE), and RD bus control signals. Using WRL and
O WRH or WR and BHE can be switched using software control.
WRL, WRH, and RD selected.
O With a 16-bit external data bus, data is written to even addresses when the
WRL signal is "L", and to the odd addresses when the WRH signal is "L". Data
is read when RD is "L".
WR, BHE, and RD selected.
Data is written when WR is "L". Data is read when RD is "L". Odd addresses are
accessed when BHE is "L". Use this mode when using an 8-bit external data bus.
O Output operation clock for the CPU.
I While the HOLD pin input is "L", the MCU is placed in the Hold state.
O The HLDA pin output is "L" while the MCU is in the hold state.
O The ALE pin can be used to latch the address.
I While the RDY pin input is "L", the MCU is in the ready state.
Rev.2.00 Oct 16, 2006 page 8 of 264
REJ03B0005-0200
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