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M32L1632512A Datasheet PDF : 54 Pages
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SGRAM
M32L1632512A
256K x 32 Bit x 2 Banks
Synchronous Graphic RAM
FEATURES
O JEDEC standard 3.3V power supply
O LVTTL compatible with multiplexed address
O Dual bank / Pulse RAS
O MRS cycle with address key programs
- CAS Latency ( 2, 3 )
- Burst Length ( 1, 2, 4, 8 & full page )
- Burst Type ( Sequential & Interleave )
O All inputs are sampled at the positive going
edge of the system clock
O Burst Read Single-bit Write operation
O DQM 0-3 for byte masking
O Auto & self refresh
O 32ms refresh period (2K cycle)
O 100 pin QFP
GENERAL DESCRIPTION
The M32L1632512A is 16, 777, 216 bits synchro-
nous high data rate Dynamic RAM organized as 2 x
262, 144 words by 32 bits, fabricated with ESMT’s
high performance CMOS technology. Synchronous
design allows precise cycle control with the use of
system clock. I/O transactions are possible on every
clock cycle. Range of operating frequencies , progra-
mmable burst length, and programmable latencies
allows the same device to be useful for a variety of
high bandwidth, high performance memory system
applications.
Write per bit and 8 columns block write improves
performance in graphic systems.
Graphic Features
O SMRS cycle
- Load mask register
- Load color register
O Write Per Bit
O Block Write (8 Columns)
ORDERING INFORMATION
Part NO.
M32L1632512A-5Q
Cycle Clock
Access tRDL
time Frequency time@CL=3 (clk)
5ns 200MHz
4.5ns
1
M32L1632512A-5SQ 5ns 200MHz
4.5ns
2
M32L1632512A-6Q 6ns 166MHz
5.5ns
1
M32L1632512A-6SQ 6ns 166MHz
5.5ns
2
M32L1632512A-7Q 7ns 143MHz
6.0ns
1
M32L1632512A-7SQ 7ns 143MHz
6.0ns
2
M32L1632512A-8Q 8ns 125MHz
6.5ns
1
M32L1632512A-8SQ 8ns 125MHz
6.5ns
2
Elite Semiconductor Memory Technology Inc.
Publication Date : Jun. 2001
Revision : 1.6
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