P4C1024L Ver la hoja de datos (PDF) - Performance Semiconductor
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P4C1024L Datasheet PDF : 8 Pages
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P4C1024L
LOW POWER 128K x 8
CMOS STATIC RAM
FEATURES
VCC Current (Commercial/Industrial)
— Operating: 70mA/85mA
— CMOS Standby: 100µA/100µA
Access Times
—55/70 (Commercial or Industrial)
Single 5 Volts ±10% Power Supply
Easy Memory Expansion Using CE1, CE2 and
OE Inputs
P4C1024L
Common Data I/O
Three-State Outputs
Fully TTL Compatible Inputs and Outputs
Advanced CMOS Technology
Automatic Power Down
Packages
—32-Pin 600 mil DIP
—32-Pin 445 mil SOP
DESCRIPTION
The P4C1024L is a 1,048,576-bit low power CMOS
static RAM organized as 128Kx8. The CMOS memory
requires no clocks or refreshing, and has equal access
and cycle times. Inputs are fully TTL-compatible. The
RAM operates from a single 5V±10% tolerance power
supply.
Access times of 55 ns and 70 ns are availale. CMOS
is utilized to reduce power consumption to a low level.
The P4C1024L device provides asynchronous opera-
tion with matching access and cycle times. Memory
locations are specified on address pins A to A . Read-
0
16
ing is accomplished by device selection (CE low and
1
CE2 high) and output enabling (OE) while write enable
(WE) remains HIGH. By presenting the address under
these conditions, the data in the addressed memory
location is presented on the data input/output pins. The
input/output pins stay in the HIGH Z state when either
CE
1
or
OE
is
HIGH
or
WE
or
CE2
is
LOW.
The P4C1024L is packaged in a 32-pin 445 mil SOP
as well as a 600 mil PDIP.
FUNCTIONAL BLOCK DIAGRAM
A
(9)
A
I/O1
I/O2
INPUT
DATA
CONTROL
262,144-
BIT
MEMORY
ARRAY
COLUMN
I/O
WE
CE1
CE2
OE
CONTROL
CIRCUIT
COLUMN
SELECT
••• •••
A
(8)
A
PIN CONFIGURATION
NC 1
A16 2
A14 3
A12 4
A7 5
A6 6
A5 7
A4 8
A3 9
A2 10
A1 11
A0 12
I/O0 13
I/O1 14
I/O2 15
GND 16
32 VCC
31 A15
30 CE2
29 WE
28 A13
27 A8
26 A9
25 A11
24 OE
23 A10
22 CE1
21 I/O7
20 I/O6
19 I/O5
18 I/O4
17 I/O3
DIP (P600), SOP (S12)
TOP VIEW
Means Quality, Service and Speed
1Q97
151
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