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M37510E3FP Datasheet PDF : 43 Pages
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MITSUBISHI MICROCOMPUTERS
7510 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
I/O PORTS
Direction Registers
The 7510 group has 41 programmable I/O pins arranged in six I/O
ports (ports P0 to P5). The I/O ports have direction registers which
determine the input/output direction of each individual pin. Each
bit in a direction register corresponds to one pin, each pin can be
set to be input or output.
When “0” is written to the bit corresponding to a pin, that pin be-
comes an input pin. When “1” is written to that bit, that pin
becomes an output pin.
If data is read from a pin which is set for output, the value of the
port output latch is read, not the value of the pin itself. Pins set to
input are floating and can read the value of the pin itself. If a pin
set to input is written to, only the port output latch is written to and
the pin remains floating.
Port Pull-up Control Registers
The 7510 group is equipped with internal pull-ups that can be en-
abled by software. Each I/O port of ports P0–P5 has an port Pi (i=
0 to 5) pull-up control register (addresses 000C16 to 001116). Each
bit of the pull-up control register controls a corresponding bit of the
port. The value written to each individual bit determines whether
the pull-up of the corresponding pin is either enabled or disabled.
When “0” is written to the pull-up control register, the pull up on the
pin is disabled. When “1” is written to the pull-up control register,
the pull-up on the pin is enabled.
After reset, all the pull-up control registers are initialized to “0016”,
disabling all the internal pull-ups.
b7
b0
Port Pi pull-up control register
(PULLPi : addresses 000C16 to 001116)
i = 0 to 5
Pi0 pull-up
Pi1 pull-up
Pi2 pull-up
Pi3 pull-up
Pi4 pull-up
Pi5 pull-up
Pi6 pull-up
Pi7 pull-up
0 : Disabled
1 : Enabled
Fig. 4 Structure of port Pi pull-up control register
Pin
Name
Input/Output
I/O Format
Non-Port Function
Related SFRs
Ref. No.
Input/output,
CMOS compatible input level
P00–P07
Port P0
(1)
individual bits
CMOS 3-state output
Input/output,
CMOS compatible input level
P10–P17
Port P1
(1)
individual bits
CMOS 3-state output
P20–P27
Port P2
Input/output,
individual bits
CMOS compatible input level Key-on wake up
CMOS 3-state output interrupt input
Interrupt control
register 2
(2)
P30/RXD2,
P31/TXD2,
P32/ SCLK2,
P33/SRDY2
P34–P37
Port P3
Input/output,
individual bits
CMOS compatible
input level
CMOS 3-state output
Serial I/O2
function I/O
Serial I/O2 control
(3)
register
(4)
Serial I/O2 status register (5)
UART control register 2
(6)
(1)
P40/INT0
Input
CMOS compatible input level External interrupt
(7)
P41/INT1
input
(8)
P42/CNTR0,
P43/CNTR1
P44/RXD1,
P45/TXD1,
P46/ SCLK1,
P47/SRDY1
Port P4
Input/output,
individual bits
CMOS compatible
input level
Timer X function I/O Timer X mode register (9)
Timer Y function I/O Timer Y mode register (8)
CMOS 3-state output
Serial I/O1
function I/O
Serial I/O1 control
(3)
register
(4)
Serial I/O1 status register (5)
UART1 control register
(6)
P50/XCOUT,
P51/XCIN
Port P5
Input/output,
individual bits
CMOS compatible input level Sub-clock generat-
CMOS 3-state output ing circuit I/O
CPU mode register
(1)
COM0–
COM15
Common
Output
LCD common output
LCD mode register
SEG0–
SEG79
Segment
Output
LCD segment output
Notes 1: For details of how to use double-function ports as function I/O ports, refer to the applicable sections.
2: Make sure that the input level at each pin is either 0 V or VCC during execution of the STP instruction.
When an input level is at an intermediate potential, a current will flow from VCC to VSS through the input-stage gate.
9
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