BS62LV2005STI-70 Ver la hoja de datos (PDF) - Brilliance Semiconductor

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BS62LV2005STI-70

Very Low Power/Voltage CMOS SRAM 256K X 8 bit

Brilliance Semiconductor 

BSI

„ SWITCHING WAVEFORMS (READ CYCLE)

READ CYCLE1 (1,2,4)

t RC

ADDRESS

D OUT

t OH

t AA

BS62LV2005

t OH

READ CYCLE2 (1,3,4)

CE1

t ACS1

CE2

D OUT

READ CYCLE3 (1,4)

ADDRESS

OE

CE1

CE2

D OUT

t ACS2

t (5)

CLZ

t RC

t AA

t OE

t OLZ

t ACS1

t (5)

CLZ1

t ACS2

t (5)

CLZ2

NOTES:

1. WE is high for read Cycle.

2. Device is continuously selected when CE1 = VIL and CE2= VIH.

3. Address valid prior to or coincident with CE1 transition low and/or CE2 transition high.

4. OE = VIL .

5. Transition is measured ± 500mV from steady state with CL = 5pF as shown in Figure 1B.

The parameter is guaranteed but not 100% tested.

(5)

t , t CHZ1 CHZ2

t OH

t (5)

OHZ

t (1,5)

CHZ1

t (2,5)

CHZ2

R0201-BS62LV2005

5

Revision 2.4

April 2002

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