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M45PE20

2 Mbit, Low Voltage, Page-Erasable Serial Flash Memory With Byte-Alterability and a 25 MHz SPI Bus Interface

STMicroelectronics 

M45PE20

MEMORY ORGANIZATION

The memory is organized as:

■ 1024 pages (256 bytes each).

■ 262,144 bytes (8 bits each)

■ 4 sectors (512 Kbits, 65536 bytes each)

Each page can be individually:

– programmed (bits are programmed from 1 to

0)

– erased (bits are erased from 0 to 1)

– written (bits are changed to either 0 or 1)

The device is Page or Sector Erasable (bits are

erased from 0 to 1).

Table 3. Memory Organization

Sector

Address Range

3

30000h

3FFFFh

2

20000h

2FFFFh

1

10000h

1FFFFh

0

00000h

0FFFFh

Figure 6. Block Diagram

Reset

W

S

C

D

Q

Control Logic

High Voltage

Generator

I/O Shift Register

Address Register

and Counter

256 Byte

Data Buffer

3FFFFh

Status

Register

10/35

10000h

00000h

256 Bytes (Page Size)

X Decoder

000FFh

First 256 Pages can

be made read-only

AI07402

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