M48T513Y-85PM1 Ver la hoja de datos (PDF) - STMicroelectronics

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M48T513Y-85PM1

3.3V-5V 4 Mbit (512Kb x8) TIMEKEEPER® SRAM

STMicroelectronics 

M48T513Y, M48T513V

Figure 4. Hardware Hookup for SMT Chip Set (1)

SNAPHAT (3)

BATTERY/CRYSTAL

32,768 Hz

CRYSTAL

LITHIUM

5V

CELL

0.1µF

A0-A18

VOUT

M48T201Y/V (2)

VCC

E

W

ECON

G

WDI

GCON

RSTIN1

RST

RSTIN2

IRQ/FT

VSS

SQW

DQ0-DQ7

0.1µF

A0-A18

VCC

M68Z512/W (2)

E

W

G

VSS

DQ0-DQ7

Note: 1. For pin connections, see individual data sheets for M48T201Y/V and M68Z512/W at www.st.com.

2. For 5V, M48T129Y (M48T201Y + M68Z512). For 3.3V, M48T129V (M48T201V + M68Z512W).

3. SNAPHAT Top ordered separately.

AI03633

READ MODE

The M48T513Y/V is in the Read Mode whenever

W (Write Enable) is high and E (Chip Enable) is

low. The unique address specified by the 17 Ad-

dress Inputs defines which one of the 524,272

bytes of data is to be accessed. Valid data will be

available at the Data I/O pins within tAVQV (Ad-

dress Access Time) after the last address input

signal is stable, providing the E and G access

times are also satisfied. If the E and G access

times are not met, valid data will be available after

the latter of the Chip Enable Access Times (tELQV)

or Output Enable Access Time (tGLQV).

The state of the eight three-state Data I/O signals

is controlled by E and G. If the outputs are activat-

ed before tAVQV, the data lines will be driven to an

indeterminate state until tAVQV. If the Address In-

puts are changed while E and G remain active,

output data will remain valid for tAXQX (Output

Data Hold Time) but will go indeterminate until the

next Address Access.

WRITE MODE

The M48T513Y/V is in the Write Mode whenever

W (Write Enable) and E (Chip Enable) are low

state after the address inputs are stable.

The start of a write is referenced from the latter oc-

curring falling edge of W or E. A write is terminated

by the earlier rising edge of W or E. The addresses

must be held valid throughout the cycle. E or W

must return high for a minimum of tEHAX from Chip

Enable or tWHAX from Write Enable prior to the ini-

tiation of another read or write cycle. Data-in must

be valid tDVWH prior to the end of write and remain

valid for tWHDX afterward. G should be kept high

during write cycles to avoid bus contention; al-

though, if the output bus has been activated by a

low on E and G a low on W will disable the outputs

tWLQZ after W falls.

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