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M68AW512M

8 Mbit (512K x16) 3.0V Asynchronous SRAM

STMicroelectronics 

M68AW512M

SUMMARY DESCRIPTION

The M68AW512M is a 8 Mbit (8,388,608 bit)

CMOS SRAM, organized as 524,288 words by 16

bits. The device features fully static operation re-

quiring no external clocks or timing strobes, with

equal address access and cycle times. It requires

a single 2.7 to 3.6V supply. This device has an au-

tomatic power-down feature, reducing the power

consumption by over 99% when deselected.

The M68AW512M is available in TSOP44 Type II

packages.

Figure 2. Logic Diagram

VCC

19

A0-A18

16

DQ0-DQ15

W

E

M68AW512M

G

UB

LB

Table 1. Signal Names

A0-A16

Address Inputs

DQ0-DQ15 Data Input/Output

E

Chip Enable

G

Output Enable

W

Write Enable

UB

Upper Byte Enable Input

LB

Lower Byte Enable Input

VCC

Supply Voltage

VSS

Ground

NC

Not Connected Internally

DU

Don’t Use as Internally Connected

VSS

AI05835c

3/19

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