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MC80C86

16-BIT CHMOS MICROPROCESSOR

Intel 

M80C86 M80C86-2

WAVEFORMS (Continued)

ASYNCHRONOUS SIGNAL RECOGNITION

271058 – 11

NOTE Setup requirements for asynchronous signals only to guarantee recognition at next CLK

BUS LOCK SIGNAL TIMING

(MAXIMUM MODE ONLY)

RESET TIMING

271058 – 12

REQUEST GRANT SEQUENCE TIMING (MAXIMUM MODE ONLY)

271058 – 13

NOTE The coprocessor may not drive the buses outside the region shown without risking contention

271058 – 14

18

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