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A62S7332E-4.5

128K X 32 Bit Synchronous High Speed SRAM with Burst Counter and Pipelined Data Output

AMIC Technology 

A63G7332 Series

Preliminary

128K X 32 Bit Synchronous High Speed SRAM

with Burst Counter and Pipelined Data Output

Features

n Fast access times: 4.2/4.5/5.0 ns (143/133/100 MHZ)

n Single +3.3V+10% or +3.3V-5% power supply

n Separate +2.5V+0.4V/-0.12V isolated output buffer

n 3.3V tolerant inputs

n Synchronous burst function

n Individual Byte Write control and Global Write

General Description

The A63G7332 is a high-speed, low-power SRAM

containing 4,194,304 bits of bit synchronous memory,

organized as 131,072 words by 32 bits.

The A63G7332 combines advanced synchronous

peripheral circuitry, 2-bit burst control, input registers,

output registers and a 128K X 32 SRAM core to provide

a wide range of data RAM applications.

The positive edge triggered single clock input (CLK)

controls all synchronous inputs passing through the

registers. Synchronous inputs include all addresses (A0 -

A16), all data inputs (I/O1 - I/O32), active LOW chip

enable ( CE ), two additional chip enables (CE2, CE2 ),

burst control inputs ( ADSC , ADSP , ADV ), byte write

enables ( BWE , BW1 , BW2 , BW3 , BW4 ) and Global

Write ( GW ). Asynchronous inputs include output enable

( OE ), clock (CLK), BURST mode (MODE) and SLEEP

mode (ZZ).

n Registered output for pipelined applications

n Three separate chip enables allow wide range of

options for CE control, address pipelining

n Selectable BURST mode

n SLEEP mode (ZZ pin) provided

n Available in 100-pin LQFP package

Burst operations can be initiated with either the address

status processor ( ADSP ) or address status controller

( ADSC ) input pin. Subsequent burst sequence burst

addresses can be internally generated by the A63G7332

and controlled by the burst advance ( ADV ) pin. Write

cycles are internally self-timed and synchronous with the

rising edge of the clock (CLK).

This feature simplifies the write interface. Individual Byte

enables allow individual bytes to be written. BW1

controls I/O1 - I/O8, BW2 controls I/O9 - I/O16, BW3

controls I/O17 - I/O24, and BW4 controls I/O25 - I/O32, all

on the condition that BWE is LOW. GW LOW causes

all bytes to be written.

PRELIMINARY (December, 1998, Version 2.1)

1

AMIC Technology, Inc.

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