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MAX19586ETN

High-Dynamic-Range, 16-Bit, 80Msps ADC with -82dBFS Noise Floor

Maxim Integrated 

High-Dynamic-Range, 16-Bit,

80Msps ADC with -82dBFS Noise Floor

ELECTRICAL CHARACTERISTICS (continued)

(AVDD = 3.3V, DVDD = 1.8V, AGND = DGND = 0, INP and INN driven differentially, internal reference CLKP and CLKN driven differentially,

CL = 5pF at digital outputs, fCLK = 80MHz, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C, unless otherwise

noted.) (Note 1)

PARAMETER

SYMBOL

CONDITIONS

TIMING SPECIFICATION (Figures 4, 5), CL = 5pF (D0–D15, DOR); CL = 15pF (DAV)

CLKP - CLKN High

CLKP - CLKN Low

tCLKP

tCLKN

(Note 2)

(Note 2)

Effective Aperture Delay

tAD

Output Data Delay

tDAT

Data Valid Delay

tDAV (Note 2)

Pipeline Latency

tP

MIN TYP MAX UNITS

5

ns

5

ns

-300

ps

3.3

ns

2.8

3.8

5.0

ns

7

Clock

Cycles

CLKP Rising Edge to DATA Not

Valid

tDNV (Note 2)

1.2

ns

CLKP Rising Edge to DATA

Guaranteed Valid

tDGV (Note 2)

6.5

ns

DATA Setup Time Before Rising

DAV

tS

Clock duty cycle = 50% (Note 2)

3

ns

DATA Hold Time After Rising

DAV

POWER SUPPLIES

Analog Power-Supply Voltage

Digital Output Power-Supply

Voltage

Analog Power-Supply Current

Digital Output Power-Supply

Current

Power Dissipation

tH

Clock duty cycle = 50% (Note 2)

AVDD

DVDD

IAVDD

IDVDD

PDISS

3

ns

3.13

3.3

3.46

V

1.7

1.8

1.9

V

320 382

mA

28

35

mA

1105 1325 mW

Note 1: ≥ +25°C guaranteed by production test, < +25°C guaranteed by design and characterization. Typical values are at TA = +25°C.

Note 2: Parameter guaranteed by design and characterization.

Note 3: AC parameter measured in a 32,768-point FFT record, where the first 2 bins of the FFT and 2 bins on either side of the carrier

are excluded.

4 _______________________________________________________________________________________

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