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MAX2308EGI
(Rev.:2001)

CDMA IF VGAs and I/Q Demodulators with VCO and Synthesizer

Maxim Integrated 

CDMA IF VGAs and I/Q Demodulators

with VCO and Synthesizer

2.4kΩ

0.068µF

47pF

0.01µF

0.01µF

10kΩ

10kΩ

10kΩ

10kΩ

33pF

2pF

33nH

33pF

33pF

2pF

33nH

33pF

VCC

47pF

I

10kΩ

Figure 1. MAX2306 Typical Operating Circuit

BYP

CP_OUT

GND

TANKL+

BYP

BYP

FM-

FM+

CDMA+

MAX2306

TANKL-

CDMA-

TANKH+

VGC

TANKH-

MODE

VCC

GND

REF

SHDN

IOUT+

VCC

DATA

EN

CLK

QOUT+

IOUT-

QOUT-

LOCK

0.01µF

VCC

0.1µF

0.01µF

680Ω

47pF

3-WIRE

10kΩ

47kΩ

VCC

FM

CDMA

DAC

VCC

Q

Voltage-Controlled Oscillator,

Buffers, and Quadrature Generation

The LO signal for downconversion is provided by a

voltage-controlled oscillator (VCO) consisting of an on-

chip differential oscillator, and an off-chip high-Q reso-

nant network. Figure 4 shows a simplified schematic of

the VCO oscillator. Multiband operation is supported by

the MAX2306 with dual VCOs. VCO_H and VCO_L are

selectable with the MODE pin or the VCO_SEL (VS)

control bit. They oscillate at twice the desired LO fre-

quency. For applications requiring an external LO, the

VCOs can be bypassed with the VCO_BYP (VB) control

bit.

The MAX2309 buffers the output of the VCO and pro-

vides this signal at the LOOUT pin. This signal is

enabled by the BUFEN (BE) control bit or by the

BUFEN control pin. The frequency of this signal is

selected by the BUF_DIV (BD) control bit, and can be

either the VCO frequency or half the VCO frequency.

Quadrature downconversion is realized by providing in-

phase (I) and quadrature-phase (Q) components of the

LO signal to the LO ports of the demodulator described

above. The quadrature LO signals are generated by

dividing the VCO output frequency using two latches.

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