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MAX2430EVKIT-SO

MAX2430 Evaluation Kits

Maxim Integrated 

MAX2430 Evaluation Kits

network to 50Ω. This ensures maximum power transfer

and good output VSWR at any selected narrow-band

frequency range of interest between 800MHz and

950MHz. The open-collector output transistor (RFOUT

pin) should see approximately a 15Ω internal load

impedance to achieve maximum power gain with the

best efficiency. The internal package inductance (5nH),

L1 (8nH), series capacitor CO, and shunt capacitor

CSH form a 15Ω to 50Ω tuneable matching network.

Resistor RC enhances stability under load mismatch

conditions and does not affect normal operation of the

circuit. The 47nH supply choke (labeled LC) provides

DC bias.

Shutdown Control

The SHDN pin is TTL/CMOS compatible and is used to

enable (or disable) the MAX2430. Table 1 lists the

options available for the shutdown control jumper, J1.

To use an external control signal, remove the shunt on

J1 completely, and connect the external signal to the

pad marked SHDN. The external control signal should

not exceed VCC. Supply current in the disabled mode

Table 1. Jumper J1 Functions

SHUNT

LOCATION

1&2

2&3

SHDN PIN

MAX2430 STATUS

Connected to VCC Enabled

Connected to GND Disabled

is typically less than 1µA.

BIAS Pin

The BIAS pin regulates the ramp-up and ramp-down times

of the output RF envelope. It can also be driven externally

to control the output power over a 15dB range. The ramp-

up/down slope is set by a capacitor connected from the

BIAS pin to ground. The EV kit comes with a 2.2nF capaci-

tor (C6), which yields an RF envelope ramp-up/down time

of approximately 10µs. The BIAS pad on the EV kit allows

the user to manipulate the MAX2430 BIAS pin. Refer to the

BIAS Pin section of the MAX2430 data sheet for more

information on output power control.

Layout Considerations

The evaluation board can serve as a guide for board lay-

out. Grounding is critical for the proper operation and sta-

bility of the MAX2430. The following considerations were

taken into account on the evaluation board. C1, C2, and

C3 should be small surface-mount capacitors, placed

directly from each effective VCC terminal to the ground

plane. Make connections short (not through vias or long

traces). C5 and C6 should be surface-mount capacitors,

located as close to the MAX2430 as possible for best

results. C2 should be next to L2. C3 should be next to LC.

LC should be perpendicular to L1, and L1 perpendicular

to L2 to ensure minimal coupling.

The evaluation board has four layers made from FR4

(εR = 4.0 to 4.6) with 1oz. copper. The first two layers

(signal and ground planes) are 14 mils apart, which pro-

vides a 50Ω characteristic impedance from 25mil-wide

traces. These trace widths are used for PIN and POUT to

maintain a 50Ω environment out to the SMA connectors.

The third layer is used for the VCC supply plane. The

fourth layer is used for the SHDN pin jumper connections

and BIAS pin signal routing. The ground metal, connect-

ed with vias on the first and second layers, acts as a

heatsink for the MAX2430, reducing internal operating

temperatures. Note that all ground and VCC plane is

removed under matching components (L1, L2, LC, RC,

CO, CSH) to minimize parasitic capacitance.

The MAX2430EVKIT-QSOP includes two large holes

under the MAX2430 to aid in attachment and removal of

the part. These holes are not necessary for proper circuit

operation.

Operation Outside the

800MHz to 950MHz Frequency Band

With minor modifications to the MAX2430 EV kit match-

ing network components, the operating frequency can

be tuned to frequencies outside the specified band.

Refer to the Applications Information section of the

MAX2430 data sheet for more information.

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