MAX3420E(2005) Ver la hoja de datos (PDF) - Maxim Integrated

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MAX3420E
(Rev.:2005)

USB Peripheral Controller with SPI Interface

Maxim Integrated 

tRISE

VOH

VOL

Figure 6. Rise and Fall Times

tL

SS

tCSS

1

SCLK

MOSI

HI-Z

MISO

tFALL

90%

10%

2

tDS

tDH

USB Peripheral Controller

with SPI Interface

Test Circuits and Timing Diagrams

MAX3420E

33Ω

D+ OR D-

TEST

POINT

CL

15kΩ

Figure 7. Load for D+/D- AC Measurements

tCL

tCH

8

9

10

tCP

tCSW

tT

16

tDO

HI-Z

Figure 8. SPI Bus Timing Diagram (Full-Duplex Mode, SPI Mode (0,0))

tL

SS

tCSW

tCL

tCH

tT

SCLK

MOSI

1

2

tDS

8

9

10

tCP

16

HI-Z

tDH

tON

tDI

tOFF

HI-Z

MISO

HI-Z

NOTES:

1) DURING THE FIRST 8 CLOCKS CYCLES, THE MOSI PIN IS HIGH IMPEDANCE AND THE SPI MASTER DRIVES DATA ONTO THE MOSI PIN. SETUP AND HOLD TIMES ARE THE SAME AS

FOR FULL-DUPLEX MODE.

2) FOR SPI WRITE CYCLES, THE MOSI PIN CONTINUES TO BE HIGH IMPEDANCE AND THE EXTERNAL MASTER CONTINUES TO DRIVE MOSI.

3) FOR SPI READ CYCLES, AFTER THE 8TH CLOCK-RISING EDGE, THE MAX3420E STARTS DRIVING THE MOSI PIN AFTER TIME tON. THE EXTERNAL MASTER MUST TURN

OFF ITS DRIVER TO THE MOSI PIN BEFORE tON TO AVOID CONTENTION. PROPAGATION DELAYS ARE THE SAME AS FOR THE MOSI PIN IN FULL-DUPLEX MODE.

Figure 9. SPI Bus Timing Diagram (Half-Duplex Mode, SPI Mode (0,0))

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