MAX3674 Ver la hoja de datos (PDF) - Maxim Integrated

Número de pieza

componentes Descripción

Lista de partido

MAX3674

High-Performance, Dual-Output, Network Clock Synthesizer

Maxim Integrated 

High-Performance, Dual-Output, Network Clock

Synthesizer

AC ELECTRICAL CHARACTERISTICS (continued)

(VCC = VCC_PLL = +3.3V ±5%, TA = -40°C to +85°C, NB = 1 (low), P = 4 (high), BYPASS = high, TEST_EN = low. Typical values are

at VCC = VCC_PLL = +3.3V, TA = +25°C, unless otherwise noted.) (Note 1)

PARAMETER

SYMBOL

CONDITIONS

MIN TYP MAX UNITS

PLL Closed-Loop Bandwidth

(Note 11)

P=2

P=4

150 to 450

kHz

75 to 225

PLL Lock Time

tLOCK (Note 12)

3

6

ms

PLL Acquisition Time When

Incrementing or Decrementing M

CONTROL TIMING (PLOAD, MR)

(Note 13)

50

μs

PLOAD Pulse Width

50

ns

MR Pulse Width

SERIAL INTERFACE I2C (SDA, SCL)

I2C Clock Frequency

fSCL

SDA Output Fall Time

tF

(Note 14)

50

ns

400

kHz

300

ns

Note 1: Specifications ≥ +25°C guaranteed by production test, < +25°C guaranteed by design and characterization.

Note 2: Inputs have pullup and pulldown resistors affecting the input current.

Note 3: Outputs terminated 50Ω to VTT = VCC - 2V. See the AC Electrical Characteristics section for Peak-to-Peak Voltage.

Note 4: PLL supply voltage must also satisfy VCC_PLL ≤ VCC + 0.3V.

Note 5: The reference clock input frequency fXTAL (and fREF_CLK) and the PLL divider M and P must match the VCO frequency

range: fVCO = fXTAL × M / P for stable PLL operation.

Note 6: The output frequency for QA and QB if NB = 1 (low) and fREF = 16MHz. With NB = 2 (high) the QB output frequency is half

the QA output frequency.

Note 7: Guaranteed by design and characterization over full temperature range (-40°C to +85°C).

Note 8: Selecting crystal oscillator as reference with fXTAL= 16MHz.

Note 9: When NB = 2 (high), the QA output has a bimodal jitter distribution. Sample size = 20,000 cycles.

Note 10: Measured as spur in frequency domain with 50mVP-P sinusoidal noise (10kHz to 10MHz) on the supply. See the Typical

Operating Characteristics.

Note 11: -3dB point of PLL transfer characteristics.

Note 12: Time period from master reset release (MR rising edge) to when PLL indicates lock (LOCK rising edge). Valid for both

crystal (after crystal oscillator stabilized) and reference clock inputs.

Note 13: Time period after incrementing or decrementing (ΔM < 5) within valid M range to when PLL indicates lock (LOCK rising

edge).

Note 14: An appropriate bus pullup resistance must be selected depending on board capacitance.

4 _______________________________________________________________________________________

Share Link: