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MAX7408

5th-Order, Lowpass, Elliptic, Switched-Capacitor Filters

Maxim Integrated 

5th-Order, Lowpass, Elliptic,

Switched-Capacitor Filters

RIPPLE

fC

TRANSITION RATIO =

fS

fC

fS

PASSBAND

fC fS

STOPBAND

FREQUENCY

VSUPPLY

0.1µF

INPUT

CLOCK

VDD

SHDN

OUT

OUTPUT

IN

COM

0.1µF

50k

MAX7408

MAX7411

CLK

MAX7412

MAX7415

OS

50k

0.1µF

GND

50k

Figure 2. Elliptic Filter Response

Clock Signal

External Clock

These SCFs are designed for use with external clocks

that have a 40% to 60% duty cycle. When using an

external clock, drive the CLK pin with a CMOS gate

powered from 0 to VDD. Varying the rate of the external

clock adjusts the corner frequency of the filter:

fC

=

fCLK

100

Internal Clock

When using the internal oscillator, the capacitance

(COSC) on CLK determines the oscillator frequency:

fOSC(kHz) = 27 ⋅ 103

COSC(pF)

Since COSC is in the low picofarads, minimize the stray

capacitance at CLK so that it does not affect the inter-

nal oscillator frequency. Varying the rate of the internal

oscillator adjusts the filter’s corner frequency by a

100:1 clock-to-corner frequency ratio. For example, an

internal oscillator frequency of 100kHz produces a

nominal corner frequency of 1kHz.

Input Impedance vs. Clock Frequencies

The MAX7408/MAX7411/MAX7412/MAX7415’s input

impedance is effectively that of a switched-capacitor

resistor (see the following equation), and is inversely

proportional to frequency. The input impedance values

determined by the equation represent the average input

impedance, since the input current is not continuous. As

a rule, use a driver with an output resistance less than

10% of the filter’s input impedance.

Figure 3. Offset Adjustment Circuit

Estimate the input impedance of the filter by using the

following formula:

ZIN =

1

(fCLK ⋅ CIN)

where fCLK = clock frequency and CIN = 1pF.

Low-Power Shutdown Mode

The MAX7408/MAX7411/MAX7412/MAX7415 have a

shutdown mode that is activated by driving SHDN low.

In shutdown mode, the filter supply current reduces to

0.2µA, and the output of the filter becomes high imped-

ance. For normal operation, drive SHDN high or con-

nect to VDD.

Applications Information

Offset (OS) and Common-Mode (COM)

Input Adjustment

COM sets the common-mode input voltage and is

biased at mid-supply with an internal resistor-divider. If

the application does not require offset adjustment, con-

nect OS to COM. For applications where offset adjust-

ment is required, apply an external bias voltage

through a resistor-divider network to OS, as shown in

Figure 3. For applications that require DC level shifting,

adjust OS with respect to COM. (Note: Do not leave OS

unconnected.) The output voltage is represented by

these equations:

VOUT = (VIN − VCOM ) + VOS

VCOM

=

VDD (typical)

2

where (VIN - VCOM) is lowpass filtered by the SCF and

OS is added at the output stage. See the Electrical

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