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MAX849

1-Cell to 3-Cell, High-Power, Low-Noise, Step-Up DC-DC Converters

Maxim Integrated 

1-Cell to 3-Cell, High-Power,

Low-Noise, Step-Up DC-DC Converters

Pin Description

PIN NAME

FUNCTION

1

AIN1

ADC’s Channel 1 Input. Analog input voltage range is 0.625V to 1.875V.

2

AIN2 ADC’s Channel 2 Input. Analog input voltage range is 0V to 2.5V.

3

REF

Reference Output. Bypass with a 0.22µF capacitor to GND.

4

GND Ground. Use for low-current ground paths. Connect to PGND with a short trace.

5

OUT

Output Sense Input. The IC is powered from OUT. Bypass to GND with a 0.1µF ceramic capacitor. Connect

OUT to POUT through a 10Ω series resistor.

6

POKIN

Power-Good Comparator Input. Connect to GND for fixed threshold (VOUT x 0.9). To adjust the threshold,

connect to a resistor divider from OUT to GND.

Dual Mode DC-DC Converter Feedback Input. Connect to GND for fixed 3.3V output voltage. Connect to

7

FB

a resistor divider from OUT to GND to adjust the output voltage. Minimize noise coupling from switching

signals to FB.

Power-Good Output. This open-drain output is pulled low when the output voltage (VOUT) drops below

8

POK

the internally set threshold (fixed threshold), or when the voltage at POKIN drops below VREF (adjustable

threshold).

9

AINSEL ADC’s Input Channel Selector. Pull low to select AIN1 and drive high to select AIN2.

10

DATA

ADC’s Serial Output. Pulsed output, RZ format. Full scale is fOSC/2 (fCLK/2 in external sync mode). The

DATA output is low when VCLK/SEL = 0V (PFM mode).

External Clock Input/Regulator’s Switching Mode Selector.

CLK/SEL = low: low-power, low-quiescent PFM mode. Delivers 100mW of output power.

CLK/SEL = high: low-noise, high-power PWM mode, switching at a constant frequency (300kHz).

11 CLK/SEL CLK/SEL = driven with external clock: low-noise, high-power, synchronized PWM mode. The internal

oscillator is synchronized to the external clock (200kHz ~ 400kHz). Turning the DC-DC converter on with

VCLK/SEL = 0V also serves as a soft-start function, since the peak inductor current is limited to 30% of the

nominal value.

12

PGND Source of the Internal N-Channel Power MOSFET. Connect to high-current ground path.

13

LX

Drain of the Internal N-Channel Power MOSFET and P-Channel Synchronous Rectifier

14

POUT

Source of the Internal P-Channel Synchronous Rectifier MOSFET. Connect an external Schottky diode from

LX to POUT. Bypass to PGND with a 0.1µF ceramic capacitor as close to the IC as possible.

15

ON2

OFF Control Input. When ON1 = 0 and ON2 = 1, the IC is off.

16

ON1

ON Control Input. When ON1 = 1 or ON2 = 0, the IC is on.

8 _______________________________________________________________________________________

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