MB88153A
■ LOCK-UP TIME
VDD
CKIN
3.0 V
External clock
stabilization wait time
XPD
VIH
Setting pin
FREQ0,
VIH
FREQ1,
ENS
CKOUT
tLK
(lock-up time )
If the XPD pin is fixed at the “H” level, the maximum time after the power is turned on until the set clock signal is
output from CKOUT pin is (the stabilization wait time of input clock to CKIN pin) + (the lock-up time “tLK”). For the
input clock stabilization time, check the characteristics of the resonator or oscillator used.
VDD
CKIN
3.0 V
External clock stabilization wait time
XPD
Setting pin VIH
FREQ0,
FREQ1,
ENS
CKOUT
VIH
tLK
(lock-up time )
When XPD pin controls the power-down, stable clock is output from CKOUT pin after becoming XPD pin = “H” level
(in the maximum after lock-Up time (tLK) ).
(Continued)
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