MB90092(1994) Ver la hoja de datos (PDF) - Fujitsu
Número de pieza
componentes Descripción
Lista de partido
MB90092 Datasheet PDF : 49 Pages
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MB90092
Pin name
VBLNK
EXS
XS
FSCO
CBCK
PDS
YOUT
YIN
COUT
CIN
VOUT
VKIN
VKOUT
VIN
Pin no.
16
17
18
20
21
22
31
32
34
35
37
38
39
40
I/O
Function
O Vertical blanking interval signal output pin
This pin outputs the Low-level signal in the vertical blanking interval.
I External circuit pins for color burst clock generator
O Connect an external crystal oscillator (14.31818 MHz for NTSC or
17.734475 MHz for PAL) and load capacitance (C) to these pins to form
a crystal oscillator circuit.
O Internal color burst clock output pin
This pin controls internal color burst clock output depending on the FO
bit of command 7.
I External color burst clock input pin
O Pin for output of the result of color burst clock phase comparison
O Luminance signal output pin
This pin outputs a signal of 2 VP-P (pedestal level 1.57 V, sink chip level
1 V).
I Luminance signal input pin for superimpose display
This pin inputs a DC-reproduced (DC-clamped) signal of 2 VP-P
(pedestal level 1.57 V, sink chip level 1 V).
O Saturation signal output pin
This pin outputs a signal at 1.57 VDC and a color burst signal amplitude
of 0.57 VP-P.
I Saturation signal input pin for superimpose display
This pin inputs a signal at 1.57 VDC and a color burst signal amplitude
of 0.57 VP-P.
O Composite video signal output pin
This pin outputs a signal of 2 VP-P (pedestal level 1.57 V, sink chip level
1 V).
I Background level control input pin for halftone background display of
external input composite video signals (input to the VIN pin and output
from the VOUT pin)
Halftone background display is controlled by setting the KID bit of
command 5 to “1”.
O Background level control output pin for halftone background display of
external input composite video signals (input to the VIN pin and output
from the VOUT pin)
Halftone background display is controlled by setting the KID bit of
command 5 to “1”.
I Composite video signal input pin for superimpose display
This pin inputs a DC-reproduced (DC-clamped) signal of 2 VP-P
(pedestal level 1.57 V, sink chip level 1 V).
(Continued)
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