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MC14175B

Quad Type D Flip-Flop

ON Semiconductor 

MC14175B

Quad Type D Flip-Flop

The MC14175B quad type D flip−flop is constructed with MOS

P−channel and N−channel enhancement mode devices in a single

monolithic structure. Each of the four flip−flops is positive−edge

triggered by a common clock input (C). An active−low reset input (R)

asynchronously resets all flip−flops. Each flip−flop has independent

Data (D) inputs and complementary outputs (Q and Q). These devices

may be used as shift register elements or as type T flip−flops for

counter and toggle applications.

Features

• Complementary Outputs

• Static Operation

• All Inputs and Outputs Buffered

• Diode Protection on All Inputs

• Supply Voltage Range = 3.0 Vdc to 18 Vdc

• Output Compatible with Two Low−Power TTL Loads or One

Low−Power Schottky TTL Load

• Functional Equivalent to TTL 74175

• These Devices are Pb−Free and are RoHS Compliant

MAXIMUM RATINGS (Voltages Referenced to VSS)

Parameter

Symbol

Value

Unit

DC Supply Voltage Range

Input or Output Voltage Range

(DC or Transient)

VDD −0.5 to +18.0 V

Vin, Vout − 0.5 to VDD

V

+ 0.5

Input or Output Current (DC or Transient) Iin, Iout

± 10

mA

per Pin

Power Dissipation per Package (Note 1)

Ambient Temperature Range

Storage Temperature Range

PD

500

mW

TA

−55 to +125 °C

−65 to +150 °C

Lead Temperature (8−Second Soldering)

260

°C

Stresses exceeding Maximum Ratings may damage the device. Maximum

Ratings are stress ratings only. Functional operation above the Recommended

Operating Conditions is not implied. Extended exposure to stresses above the

Recommended Operating Conditions may affect device reliability.

1. Temperature Derating: Plastic “P and D/DW”

Packages: – 7.0 mW/_C From 65_C To 125_C

This device contains protection circuitry to guard against damage due to high

static voltages or electric fields. However, precautions must be taken to avoid

applications of any voltage higher than maximum rated voltages to this

high−impedance circuit. For proper operation, Vin and Vout should be constrained

to the range VSS v (Vin or Vout) v VDD.

Unused inputs must always be tied to an appropriate logic voltage level

(e.g., either VSS or VDD). Unused outputs must be left open.

1

1

http://onsemi.com

MARKING

DIAGRAMS

PDIP−16

P SUFFIX

16

MC14175BCP

AWLYYWWG

CASE 648

1

SOIC−16 16

D SUFFIX

CASE 751B

1

14175BG

AWLYWW

16

SOEIAJ−16

F SUFFIX

CASE 966

MC14175B

ALYWG

1

1

A

= Assembly Location

WL, L = Wafer Lot

YY, Y = Year

WW, W = Work Week

G

= Pb−Free Package

ORDERING INFORMATION

Device

MC14175BCPG

Package

PDIP−16

(Pb−Free)

Shipping†

500 Units/Rail

MC14175BDG

SOIC−16

(Pb−Free)

MC14175BDR2G SOIC−16

(Pb−Free)

48 Units/Rail

2500/Tape & Reel

MC14175BFELG SOEIAJ−16 2000/Tape & Reel

(Pb−Free)

†For information on tape and reel specifications,

including part orientation and tape sizes, please

refer to our Tape and Reel Packaging Specifications

Brochure, BRD8011/D.

© Semiconductor Components Industries, LLC, 2011

1

June, 2011 − Rev. 7

Publication Order Number:

MC14175B/D

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