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MC145488

Low-Voltage Cmos Octal Transceiver

Motorola => Freescale 

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

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Low-Voltage CMOS Octal

Transceiver

With 5V-Tolerant Inputs and Outputs

(3-State, Non-Inverting)

MC74LCX2245

The MC74LCX2245 is a high performance, non–inverting octal

transceiver operating from a 2.7 to 3.6V supply. High impedance TTL

compatible inputs significantly reduce current loading to input drivers

while TTL compatible outputs offer improved switching noise

performance. A VI specification of 5.5V allows MC74LCX2245 inputs to

be safely driven from 5V devices. The MC74LCX2245 is designed to

reduce output overshoot and undershoot and is suitable for memory

address driving and all TTL level bus oriented transceiver applications;

especially those requiring the very quiet outputs.

Current drive capability is 12mA at both A and B ports. The

Transmit/Receive (T/R) input determines the direction of data flow

through the bi–directional transceiver. Transmit (active–HIGH) enables

data from A ports to B ports; Receive (active–LOW) enables data from B

to A ports. The Output Enable input, when HIGH, disables both A and B

ports by placing them in a HIGH Z condition.

LOW–VOLTAGE CMOS

OCTAL TRANSCEIVER

DW SUFFIX

20–LEAD PLASTIC SOIC

CASE 751D–04

• Designed for 2.7 to 3.6V VCC Operation

• 5V Tolerant — Interface Capability With 5V TTL Logic

• Supports Live Insertion and Withdrawal

• IOFF Specification Guarantees High Impedance When VCC = 0V

• LVTTL Compatible

• LVCMOS Compatible

• 12mA Balanced Output Sink and Source Capability

• Near Zero Static Supply Current in All Three Logic States (10µA)

Substantially Reduces System Power Requirements

• Latchup Performance Exceeds 500mA

• ESD Performance: Human Body Model >2000V; Machine Model >200V

M SUFFIX

20–LEAD PLASTIC SOIC EIAJ

CASE 967–01

SD SUFFIX

20–LEADPLASTIC SSOP

CASE 940C–03

DT SUFFIX

20–LEAD PLASTIC TSSOP

CASE 948E–02

VCC OE B0 B1 B2 B3 B4 B5 B6 B7

20 19 18 17 16 15 14 13 12 11

1 2 3 4 5 6 7 8 9 10

T/R A0 A1 A2 A3 A4 A5 A6 A7 GND

Figure 1. 20–Lead Pinout

(Top View)

PIN NAMES

Pins

Function

OE

T/R

A0–A7

B0–B7

Output Enable Input

Transmit/Receive Input

Side A 3–State Inputs or 3–State

Outputs

Side B 3–State Inputs or 3–State

Outputs

This document contains information on a product under development. Motorola reserves the right to change or

discontinue this product without notice.

1/97

© Motorola, Inc. 1997

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