MC14536B Ver la hoja de datos (PDF) - Motorola => Freescale
Número de pieza
componentes Descripción
Lista de partido
MC14536B Datasheet PDF : 13 Pages
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500 µF
VDD
ID
0.01 µF
CERAMIC
PULSE
GENERATOR
SET
RESET OUT 1
8–BYPASS
CL
IN1
C INH
MONO IN OUT
OSC INH 2
CL
A
B
C DECODE
D
OUT
CL
VSS
20 ns
20 ns
90% 50%
10%
50%
DUTY CYCLE
Figure 6. Power Dissipation Test
Circuit and Waveform
PULSE
GENERATOR
20 ns
VDD
SET
OUT 1
RESET
8–BYPASS
IN1
C INH
MONO IN OUT
OSC INH 2
A
B
C DECODE
D
OUT
VSS
IN1
tWL
OUT
tPLH
CL
20 ns
90%
10%
tTLH
50%
tWH
50%
tPHL
tTHL
Figure 7. Switching Time Test Circuit and Waveforms
FUNCTIONAL TEST SEQUENCE
Test function (Figure 8) has been included for the reduc-
tion of test time required to exercise all 24 counter stages.
This test function divides the counter into three 8–stage
sections and 255 counts are loaded in each of the 8–stage
sections in parallel. All flip–flops are now at a “1”. The count-
er is now returned to the normal 24–stages in series configu-
ration. One more pulse is entered into In1 which will cause
the counter to ripple from an all “1” state to an all “0” state.
PULSE
GENERATOR
VDD
SET
RESET OUT 1
8–BYPASS
IN1
C INH
MONO IN OUT
OSC INH 2
A
B
C DECODE
D
OUT
VSS
Figure 8. Functional Test Circuit
FUNCTIONAL TEST SEQUENCE
Inputs
Outputs
Comments
Decade Out
In1
Set Reset 8–Bypass Q1 thru Q24
1
0
1
1
0
All 24 stages are in Reset mode.
1
1
1
1
0
Counter is in three 8 stage sections in parallel mode.
0
1
1
1
0
First “1” to “0” transition of clock.
1
0
—
1
1
1
—
—
255 “1” to “0” transitions are clocked in the counter.
0
1
1
1
1
The 255 “1” to “0” transition.
0
0
0
0
1
Counter converted back to 24 stages in series mode.
Set and Reset must be connected together and simultaneously
go from “1” to “0”.
1
0
0
0
0
0
0
0
1
In1 Switches to a “1”.
0
Counter Ripples from an all “1” state to an all “0” state.
MC14536B
8
MOTOROLA CMOS LOGIC DATA
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