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MC1494

Linear Four-Quadrant Multiplier

ON Semiconductor 

MC1494

illustrates the theoretical simplicity of such an approach and

a practical realization is shown in Figure 23.

The characteristic “failure” mode of the divide circuit is

latch–up. One way it can occur is if VX is allowed to go

negative, or in some cases, if VX approaches zero.

Figure 22 illustrates why this is so. For VX > 0 the transfer

function through the multiplier is noninverting. Its output is

fed to the inverting input of the op amp Thus, operation is in

the negative feedback mode and the circuit is DC stable.

VX

KVX VY

+

+

+ VY

MC1494

VZ

+

-

-

+

VZ = -KVXVY

or

VO =

-VZ

KVX

VO

Figure 22. Basic Divide Circuit Using Multiplier

Should VX change polarity, the transfer function through

the multiplier becomes inverting, the amplifier has positive

feedback and latch–up results. The problem resulting from

VX being near zero is a result of the transfer through the

multiplier being near zero. The op amp is then operating

with a very high closed–loop gain and error voltages can

thus become effective in causing latch–up.

The other mode of latch–up results from the output

voltage of the op amp exceeding the rated common mode

input voltage of the multiplier. The input stage of the

multiplier becomes saturated, phase reversal results, and the

circuit is latched up. The circuit of Figure 23 protects against

this happening by clamping the output swing of the op amp

to approximately ± 10.7 V. Five percent tolerance, 10 V

zeners are used to assure adequate output swing but still limit

the output voltage of the op amp from exceeding the

common mode input range of the MC1494.

Setting up the divide circuit for reasonably accurate

operation is somewhat different from the procedure for the

multiplier itself. One approach, however, is to break the

feedback loop, null out the multiplier circuit, and then close

the loop.

30 k

62 k

10 pF

510

11

9

+

12 7

MC1494

8

14

1

3

10

VX

+

6

10 pF

5 15 13 4 P1 20 k 2

510

P3 50 k

-15 V +15 V

P2 20 k

RL

50 k

22 k

10 pF

2

-

MC1741CP1 6

16 k

3+

4

7

VZ

1N5240A

(10 V)

or

VO Equivalent

VO =

-10 VZ

VX

+15 V -15 V

0 < VX < +10 V

-10 V ≤ VZ ≤ +10 V

Figure 23. Practical Divide Circuit

A simpler approach, since it does not involve breaking the

loop (thus making it more practical on a production basis),

is:

1. Set VZ = 0 V and adjust the output offset potentiometer

(P3) until the output voltage (VO) remains at some (not

necessarily zero) constant value as VX is varied

between +1.0 V and +10 V.

2. Maintain VZ at 0 V, set VX at +10 V and adjust the

Y input offset potentiometer (P1) until VO = 0 V.

3. With VX = VZ, adjust the X input offset potentiometer

(P2) until the output voltage remains at some (not

necessarily –10 V) constant value as VZ = VX is varied

between +1.0 V and +10 V.

4. Maintain VX = VZ and adjust the scale factor

potentiometer (RL) until the average value of VO is

–10 V as VZ = VX is varied between +1.0 V and +10 V.

5. Repeat steps 1 through 4 as necessary to achieve

optimum performance.

Users of the divide circuit should be aware that the

accuracy to be expected decreases in direct proportion to the

denominator voltage. As a result, if VX is set to 10 V and

0.5% accuracy is available, then 5% accuracy can be

expected when VX is only 1.0 V.

In accordance with an earlier statement, VX may have

only one polarity (positive) while VZ may be either polarity.

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