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74AC257

Quad 2−Input Multiplexer with 3−State Outputs

ON Semiconductor 

OE

I0a

MC74AC257, MC74ACT257

I1a

I0b

I1b

I0c

I1c

I0d

I1d

S

NOTE:

Za

Zb

Zc

Zd

This diagram is provided only for the understanding of logic operations

and should not be used to estimate propagation delays.

Figure 3. Logic Diagram

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3

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