AD7701(RevD) Ver la hoja de datos (PDF) - Analog Devices
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AD7701 Datasheet PDF : 16 Pages
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AD7701
PIN FUNCTION DESCRIPTION
Pin Mnemonic Description
1
2
3
4, 17
5
6
7
8
9
10
11
12
13
14
15
16
18
19
20
MODE
CLKOUT
CLKIN
SC1, SC2
DGND
DVSS
AVSS
AGND
AIN
VREF
SLEEP
BP/UP
CAL
AVDD
DVDD
CS
DRDY
SCLK
SDATA
Selects the Serial Interface Mode. If MODE is tied to –5 V, the AD7701 will operate in the asynchronous
communications (ac) mode. The SCLK pin is configured as an input, and data is transmitted in two bytes,
each with one start bit and two stop bits. If MODE is tied to DGND, the synchronous external clocking
(SEC) mode is selected. SCLK is configured as an input, and the output appears without formatting, the
MSB coming first. If MODE is tied to +5 V, the AD7701 operates in the synchronous self-clocking (SSC)
mode. SCLK is configured as an output, with a clock frequency of fCLKlN/4 and 25% duty-cycle.
Clock Output to generate an Internal Master Clock by connecting a crystal between CLKOUT and CLKIN.
If an external clock is used, CLKOUT is not connected.
Clock Input for External Clock.
System Calibration Pins. The state of these pins, when CAL is taken high, determines the type of calibration
performed.
Digital Ground. Ground reference for all digital signals.
Digital Negative Supply, –5 V nominal.
Analog Negative Supply, –5 V nominal.
Analog Ground. Ground reference for all analog signals.
Analog Input.
Voltage Reference Input, +2.5 V nominal. This determines the value of positive full-scale in the unipolar
mode and of both positive and negative full-scale in the bipolar mode.
Sleep mode pin. When this pin is taken low, the AD7701 goes into a low-power mode with typically 10 µW
power consumption.
Bipolar/Unipolar Mode Pin. When this pin is low, the AD7701 is configured for a unipolar input range going
from AGND to VREF. When Pin 12 is high, the AD7701 is configured for a bipolar input range, ± VREF.
Calibration Mode Pin. When CAL is taken high for more than 4 cycles, the AD7701 is reset and performs a
calibration cycle when CAL is brought low again. The CAL pin can also be used as a strobe to synchronize
the operation of several AD7701s.
Analog Positive Supply, +5 V nominal.
Digital Positive Supply, +5 V nominal.
Chip Select Input. When CS is brought low, the AD7701 will begin to transmit serial data in a format deter-
mined by the state of the MODE pin.
Data Ready output. DRDY is low when valid data is available in the output register. It goes high after transmission
of a word is completed. It also goes high for four clock cycles when a new data word is being loaded into the out-
put register, to indicate that valid data is not available, irrespective of whether data transmission is complete or not.
Serial Clock Input/Output. The SCLK pin in configured as an input or output, dependent on the type of se-
rial data transmission that has been selected by the MODE pin. When configured as an output in the syn-
chronous self-clocking mode, it has a frequency of fCLKIN/4 and a duty cycle of 25%.
Serial Data Output. The AD7701’s output data is available at this pin as a 16-bit serial word. The transmis-
sion format is determined by the state of the MODE pin.
PIN CONFIGURATIONS
DIP, Cerdip, SOIC
SSOP
MODE 1
20 SDATA
CLKOUT 2
19 SCLK
CLKIN 3
18 DRDY
SC1 4
17 SC2
AD7701
DGND 5
16 CS
TOP VIEW
DVSS 6 (Not to Scale) 15 DVDD
AVSS 7
14 AVDD
AGND 8
13 CAL
AIN 9
VREF 10
12 BP/UP
11 SLEEP
MODE 1
28 SDATA
CLKOUT 2
27 SCLK
CLKIN 3
26 DRDY
SC1 4
25 SC2
DGND 5
24 CS
NC 6
NC 7
DVSS 8
NC 9
23 NC
AD7701 22 NC
TOP VIEW
(Not to Scale)
21
NC
20 DVDD
AVSS 10
19 AVDD
NC 11
18 NC
AGND 12
17 CAL
AIN 13
VREF 14
16 BP/UP
15 SLEEP
NC = NO CONNECT
ORDERING GUIDE
Model
Temperature
Range
Linearity
Package
Error (% FSR) Options*
AD7701AN
AD7701BN
AD7701AR
AD7701BR
AD7701ARS
AD7701AQ
AD7701BQ
AD7701SQ
AD7701TQ
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–55°C to +125°C
–55°C to +125°C
0.003
0.0015
0.003
0.0015
0.003
0.003
0.0015
0.003
0.0015
N-20
N-20
R-20
R-20
RS-28
Q-20
Q-20
Q-20
Q-20
NOTES
*N = Plastic DIP; Q = Cerdip; R = SOIC; RS = SSOP.
–4–
REV. D
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