OKI Semiconductor
FEDL7041-04
ML7041
TIMING DIAGRAM
Transmit Side PCM Timing (Normal Synchronous Interface)
BCLK
SYNC
PCMOUT
0
1
2
3
4
5
6
7
tSB
tWS
tXD1
tXD2
MSB
tSDX
When tSB >= 0, the Delay of the MSB is defined as tXD1.
When tSB < 0, the Delay of the MSB is defined as tSDX.
Transmit Side PCM Timing (Short Frame Synchronous Interface)
BCLK
0
1
2
3
4
5
6
7
tSB
tBS
SYNC
tWS
tXD1
tXD2
MSB
PCMOUT
8
9
10
tXD3
LSB
8
9
10
tXD3
LSB
Receive Side PCM Timing (Normal Synchronous Interface)
BCLK
0
1
2
3
4
5
6
7
8
9
10
tSB
tWS
SYNC
tRD1
tRD2
tRD3
MSB
LSB
PCMIN
tSDR
Receive Side PCM Timing (Short Frame Synchronous Interface)
BCLK
0
1
2
3
4
5
6
7
8
9
10
tSB
tBS
SYNC
tWS
tRD1
tRD2
tRD3
MSB
LSB
PCMIN
Figure 6 PCM Interface Timing
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