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ML7048

3-Channel Single Rail CODEC

Oki Electric Industry 

1Semiconductor

PEDL7048-01-01

ML7048-01

APPLICATION NOTE

Pull-up Resistor for the DOUT Pin

Use an optimal value of pull-up resistor for the DOUT pin considering the frequency and load capacitance of

BCLK used. If a small value of pull-up resistor is used, the distortion characteristics may be degraded and current

consumption also may be increased.

Select a pull-up resistance referencing the following calculation conditions.

Calculation conditions:

If SYNC and BCLK have risen and data is looped between DOUT and DIN, data can be normally input and

output.

1 − 20ns

R PULL

=

4 × FBCLK

CL

(Ω)

FBCLK : Frequency of BCLK

CL : Load capacitance of DOUTn

20ns : Internal delay

XSYNC, RSYNC

BCLK

DOUTn

t = RPULL × CL

Calculation example:

BCLK (Hz)

64k

128k

256k

512k

1.024M

2.048M

CL = 10 pF

388.6

193.3

95.7

46.8

22.4

10.2

RPULL (kΩ)

CL = 20 pF

CL = 50 pF

194.3

77.7

96.7

38.7

47.8

19.1

23.4

9.4

11.2

4.5

5.1

2.0

CL = 100 pF

38.9

19.3

9.7

4.7

2.2

1.0

Selection of resistance value:

If the calculated resistance is more than 100 kΩ, use a 100 kΩ resistor.

Since the calculated resistance +10% is allowable, you can use a typical resistance a little higher than the

calculated resistance.

16/20

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