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ML65T541

3.3V High Speed Octal Buffer/Line Driver

Micro Linear Corporation 

FUNCTIONAL DESCRIPTION

The ML65T541 is a very high speed non-inverting buffer/

line driver with three-state outputs which is ideally suited

for bus-oriented applications. It provides a low propagation

delay by using an analog design approach (a high speed

unity gain buffer), as compared to conventional digital

approaches. The ML65T541 follows the pinout and

functionality of the industry standard FCT541 series of

buffers/line drivers and is intended to replace them in

designs where the propagation delay is a critical part of

the system design considerations. The ML65T541 is capable

of driving load capacitances several times larger than its

input capacitance. It is configured so that the Ai inputs go

to the Bi outputs when enabled by OE1/OE2

These unity gain analog buffers achieve low propagation

delays by having the output follow the input with a small

offset. When the output reaches one VBE off the rail, the

PMOS pull-up is activated to drive the output the rest of

the way. All inputs and outputs have Schottky clamp diodes

to handle undershoot or overshoot noise suppression in

unterminated applications. All outputs have ground

bounce suppression (typically < 400mV), high drive

output capability with almost immediate response to the

input signal, and low output skew.

The IOL current drive capability of a buffer/line driver is

often interpreted as a measure of its ability to sink current

in a dynamic sense. This may be true for CMOS buffer/

line drivers, but it is not true for the ML65T541. This is

because their sink and source current capability depends

ML65T541

on the voltage difference between the output and the input.

The ML65T541 can sink or source more than 100mA to a

load when the load is switching due to the fact that during

the transition, the difference between the input and output

is large. IOL is only significant as a DC specification, and

is 5mA.

ARCHITECTURAL DESCRIPTION

Until now, buffer/line drivers have been implemented in

CMOS logic and made to be TTL compatible by sizing the

input devices appropriately. In order to buffer large

capacitances with CMOS logic, it is necessary to cascade

an even number of inverters, each successive inverter

larger than the preceding, eventually leading to an inverter

that will drive the required load capacitance at the required

frequency. Each inverter stage represents an additional

delay in the gating process because in order for a single

gate to switch, the input must slew more than half of the

supply voltage. The best of these CMOS buffers has

managed to drive a 50pF load capacitance with a delay of

3.2ns. Micro Linear has produced a dual quad buffer/line

driver with a delay of less than 2ns by using a unique

circuit architecture that does not require cascaded logic

gates. The ML65T541 uses a feedback technique to

produce an output that follows the input. If the output

voltage is not close to the input, then the feedback

circuitry will source or sink enough current to the load

capacitance to correct the discrepancy.

The basic architecture of the ML65T541 is shown in

Figure 5. It is implemented on a 1.5µm BiCMOS process.

R8

Q1

INV

R1

IN

VCC

Q2

M1

R3

R4

Q4

Q3

Q5

R5

R2

Q6

R6

R7

Q7

GND

Figure 5. One buffer cell of the ML65T541

OUT

5

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