MM1250 Ver la hoja de datos (PDF) - Mitsumi

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MM1250

I2C Bus Video Switch Monolithic IC

Mitsumi 

MITSUMI

I2C Bus

I2C Bus Video Switch MM1250

SDA

SCL

MSB

LSB

MSB

S

1 2 3 4 5 6 7 8 ACK 1

2 ACK P

S:Start Condition

P:Stop Condition

ACK:Acknowledge

The I2C bus (Inter IC Bus) is a bus system developed by Philips.

Data is transferred on two lines, SDA and SCL.

Data is transferred in byte units, and MSB is first from start condition.

1. Data format

Slave address

R/W

Control bits

S

A

AP

10010010

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

Address byte

Control byte

The first 7 bits of the address byte is the salve address, and the last bit is allocated as R/W bit. On

MM1250XD, 92H is used for the slave address and 0 (write only) for the R/W bit.

The A at the 9th bit is an acknowledge signal added for verification from slave.

2. Control byte format

Control byte configuration on MM1250XD is allocated as shown in the table below.

Each bit is set at "0" when power is turned on.

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

OUT Mute SW2 SW1 SW0

: Don't Care

SW V, L, R control

Control

SW1 SW0

0

0

0

1

1

0

1

1

Control results

MODE1 VOUT LOUT

TV

VTV

LTV

E1

VE1 LE1

E2

VE2 LE2

TV

VTV

LTV

ROUT

RTV

RE1

RE2

RTV

Audio Mute control

Mute

0

1

LOUT

SW•L

Mute

ROUT

SW•R

Mute

Out Port control

OUT Pin 13 status

0

Low

1

Open

SW Y, C control

Control

MODE1 S4

TV

-

A

E1

B

E2

-

TV

-

A

E1

B

E2

-

SW2

0

0

0

0

1

1

1

1

Control results

Mode2 SW•Y SW•C

Comp YIN

CIN

Comp YIN

CIN

S

VE1

SCIN

Comp YIN

CIN

TH

VTV

VTV

TH

VE1 VE1

S

VE1

SCIN

TH

VE2 VE2

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