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MM74C76

Dual J-K Flip-Flops with Clear and Preset

Fairchild Semiconductor 

October 1987

Revised January 1999

MM74C73 • MM74C76

Dual J-K Flip-Flops with Clear and Preset

General Description

The MM74C73 and MM74C76 dual J-K flip-flops are mono-

lithic complementary MOS (CMOS) integrated circuits con-

structed with N- and P-channel enhancement transistors.

Each flip-flop has independent J, K, clock and clear inputs

and Q and Q outputs. The MM74C76 flip flops also include

preset inputs and are supplied in 16 pin packages. This

flip-flop is edge sensitive to the clock input and change

state on the negative going transition of the clock pulse.

Clear or preset is independent of the clock and is accom-

plished by a low level on the respective input.

Features

s Supply voltage range: 3V to 15V

s Tenth power TTL compatible: Drive 2 LPTTL loads

s High noise immunity: 0.45 VCC (typ.)

s Low power: 50 nW (typ.)

s Medium speed operation: 10 MHz (typ.)

Applications

• Automotive

• Data terminals

• Instrumentation

• Medical electronics

• Alarm systems

• Industrial electronics

• Remote metering

• Computers

Ordering Code:

Order Number

MM74C73N

MM74C76M

MM74C76N

Package Number

Package Description

N14A

14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide

M16A

16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow

N16E

16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide

Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.

Connection Diagrams

MM74C73

MM74C76

Note: A logic “0” on clear sets Q to logic “0”.

Top View

Note: A logic “0” on clear sets Q to a logic “0”.

Note: A logic “0” on preset sets Q to a logic “1”.

Top View

© 1999 Fairchild Semiconductor Corporation DS005884.prf

www.fairchildsemi.com

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