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MM74HC573SJ

8-Bit Shift Registers with Input Latches and 3-STATE Serial Output

Fairchild Semiconductor 

September 1983

Revised May 2005

MM74HC573

3-STATE Octal D-Type Latch

General Description

The MM74HC573 high speed octal D-type latches utilize

advanced silicon-gate P-well CMOS technology. They pos-

sess the high noise immunity and low power consumption

of standard CMOS integrated circuits, as well as the ability

to drive 15 LS-TTL loads. Due to the large output drive

capability and the 3-STATE feature, these devices are ide-

ally suited for interfacing with bus lines in a bus organized

system.

When the LATCH ENABLE(LE) input is HIGH, the Q out-

puts will follow the D inputs. When the LATCH ENABLE

goes LOW, data at the D inputs will be retained at the out-

puts until LATCH ENABLE returns HIGH again. When a

HIGH logic level is applied to the OUTPUT CONTROL OC

input, all outputs go to a HIGH impedance state, regardless

of what signals are present at the other inputs and the state

of the storage elements.

The 74HC logic family is speed, function and pinout com-

patible with the standard 74LS logic family. All inputs are

protected from damage due to static discharge by internal

diode clamps to VCC and ground.

Features

s Typical propagation delay: 18 ns

s Wide operating voltage range: 2 to 6 volts

s Low input current: 1 PA maximum

s Low quiescent current: 80 PA maximum (74HC Series)

s Compatible with bus-oriented systems

s Output drive capability: 15 LS-TTL loads

Ordering Code:

Order Number Package Number

Package Description

MM74HC573WM

M20B

20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide

MM74HC573SJ

M20D

20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

MM74HC573MTC

MTC20

20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide

MM74HC573N

N20A

20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide

Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Connection Diagram

Truth Table

Output

Latch

Data

Output

Control

Enable

L

H

H

H

L

H

L

L

L

L

X

Q0

H

X

X

Z

H HIGH Level

L LOW Level

Q0 Level of output before steady-state input conditions were established.

Z High Impedance

X Don't Care

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© 2005 Fairchild Semiconductor Corporation DS005212

www.fairchildsemi.com

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