MP1531 Ver la hoja de datos (PDF) - Monolithic Power Systems

Número de pieza

componentes Descripción

Lista de partido

MP1531

Low Power, Triple Output Step-Up Plus Charge Pump for TFT Bias

Monolithic Power Systems 

MP1531 – LOW POWER, TRIPLE OUTPUT STEP-UP PLUS CHARGE PUMP FOR TFT BIAS

The output filter zero is given in hertz by:

fFILTERZERO

=

1

2 × π × RESR

× C2

Where RESR is the equivalent series resistance

of the output capacitor.

With all boost regulators the right half plane

zero (RHPZ) is given in hertz by:

fRHPZ

=

⎜⎜⎝⎛

VIN

VMAIN

⎟⎟⎠⎞

2

×

VMAIN

2 × π × ILOAD

× L1

Error Amplifier Compensation

To stabilize the feedback loop dynamics the

error amplifier compensation is as follows:

fPOLE1

≈

2×

1

π × 10 6

×

C3

f ZERO1

=

1

2π × R3 × C3

Where R3 and C3 are part of the compensation

network in Figure 3. A good start is 5.6kΩ and

10nF. This combination gives about 70° of

phase margin and bandwidth of about 35KHz

for most load conditions. Increasing R3 and/or

reducing C3 increases the loop bandwidth and

improves the load transient.

Linear Regulator Compensation

The positive or negative regulated voltages of

two linear regulators are controlled by a

transconductance amplifier and a P-channel or

N-Channel pass transistor respectively. The DC

gain of either LDO is approximately 100dB with

a slight dependency on load current. The output

capacitor (CLDO) and resistance load (RLOAD)

make-up the dominant pole.

fLDOPOLE1

=

1

2 × π × RLOAD

× CLDO

The pass transistor’s internal pole is about

10Hz to 30Hz. To compensate for the two pole

system and add more phase and gain margin, a

lead-lag resistor capacitor network is

necessary.

For the positive linear regulator:

fPOSPOLE1

=

2 × π × (R10

1

+ R9

|| R8)× C7

fPOSZERO1

=

2×

1

π × (R10 + R9)× C7

For the negative linear regulator:

fNEGPOLE1

=

2 × π × (R6

1

+ R7

||

R5)× C9

fNEGZERO1

=

2×

1

π × (R6 + R7)× C9

fPOSPOLE1 and fNEGPOLE1 are necessary to cancel

out the zero created by the equivalent series

resistance (RLDOESR) of the output capacitor.

fLDOZERO

=

1

2 × π × RLDOESR

× CLDO

For component values shown in Figure 3 a 10Ω

and 56pF RC network gives about 45° of phase

margin and a bandwidth of about 35KHz on

both regulators.

Layout Considerations

Careful PC board layout is important to

minimize ground bounce and noise. First, place

the main boost converter inductor, output diode

and output capacitor as close to the SW and

PGND pins as possible with wide traces. Then

place ceramic bypass capacitors near IN, IN2

and IN3 pins to the PGND pin. Keep the

charge-pump circuitry close to the IC with wide

traces. Locate all FB resistive dividers as close

to their respective FB pins as possible.

Separate GND and PGND areas and connect

them at one point as close to the IC as

possible. Avoid having sensitive traces near the

SW node and high current lines. Refer to the

MP1531 demo board for an example of proper

board layout.

MP1531 Rev. 1.2

www.MonolithicPower.com

10

5/22/2006

MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited.

© 2006 MPS. All Rights Reserved.

Share Link: