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MPC9893FA

Low Voltage PLL Intelligent Dynamic Clock (IDCS) Switch

Motorola => Freescale 

Freescale Semiconductor, Inc.

MPC9893

VCC

VCC÷2

GND

VCC

VCC÷2

GND

tSK(O)

The pin- to- pin skew is defined as the worst case difference

in propagation delay between any similar delay path within a

single device

Figure 12. Output--to--output Skew tSK(O)

VCC

VCC÷2

GND

tP

T0

DC = tP/T0 x 100%

The time from the PLL controlled edge to the non controlled

edge, divided by the time between PLL controlled edges,

expressed as a percentage

Figure 14. Output Duty Cycle (DC)

CLK0,

CLK1

FB

t(∅)

VCC

VCC÷2

GND

VCC

VCC÷2

GND

Figure 13. Propagation delay (t(∅), static phase

offset) test reference

CLK0, 1

FB

TJIT(∅) = |T0 - T1mean|

The deviation in t0 for a controlled edge with respect to a t0 mean in a

random sample of cycles

Figure 15. I/O Jitter

TN

TN+1

TJIT(CC) = |TN - TN+1|

The variation in cycle time of a signal between adjacent cycles, over a

random sample of adjacent cycle pairs

Figure 16. Cycle--to--cycle Jitter

VCC=3.3V VCC=2.5V

2.4

1.8V

0.55

0.6V

tF

tR

Figure 18. Output Transition Time Test Reference

TJIT(PER) = |TN - 1/f0|

T0

The deviation in cycle time of a signal with respect to the ideal period over

a random sample of cycles

Figure 17. Period Jitter

TIMING SOLUTIONS

For More Informa1t1ion On This Product,

Go to: www.freescale.com

MOTOROLA

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