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MPC961C

Low Voltage Zero Delay Buffer

Motorola => Freescale 

MOTOROLA

Freescale Semiconductor, Inc.

SEMICONDUCTOR TECHNICAL DATA

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by MPC961C/D

Low Voltage Zero Delay

Buffer

The MPC961 is a 2.5V or 3.3V compatible, 1:18 PLL based zero delay

buffer. With output frequencies of up to 200MHz, output skews of 150ps

the device meets the needs of the most demanding clock tree

applications.

• Fully Integrated PLL

• Up to 200MHz I/O Frequency

• LVCMOS Outputs

• Outputs Disable in High Impedance

• LVCMOS Reference Clock Options

• LQFP Packaging

• ±50ps Cycle–Cycle Jitter

• 150ps Output Skews

The MPC961 is offered with two different input configurations. The

MPC961C offers an LVCMOS reference clock while the MPC961P offers

an LVPECL reference clock.

When pulled high the OE pin will force all of the outputs (except QFB)

into a high impedance state. Because the OE pin does not affect the QFB

output, down stream clocks can be disabled without the internal PLL

losing lock.

The MPC961 is fully 2.5V or 3.3V compatible and requires no external

loop filter components. All control inputs accept LVCMOS compatible

levels and the outputs provide low impedance LVCMOS outputs capable

W of driving terminated 50 transmission lines. For series terminated lines

the MPC961 can drive two lines per output giving the device an effective

fanout of 1:36. The device is packaged in a 32 lead LQFP.

MPC961C

LOW VOLTAGE

ZERO DELAY BUFFER

FA SUFFIX

32–LEAD LQFP PACKAGE

CASE 873A–02

Q0

Q1

CCLK

Ref PLL

50k

100 – 200 MHz

O

Q2

50 – 100 MHz

1

Q3

FB_IN

FB

50k

Q14

F_RANGE

50k

Q15

Q16

OE

50k

QFB

The MPC961C requires an external RC filter for the analog power supply pin VCCA. Please see applications section for details.

Figure 1. MPC961C Logic Diagram

03/01

© Motorola, Inc. 2001

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