MSM7581 Ver la hoja de datos (PDF) - Oki Electric Industry
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MSM7581 Datasheet PDF : 18 Pages
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MSM7581
SIA1, SOA1
ADPCM serial data input (SIA1) and output (SOA1) pins for Channel 1.
SOA1 is an open-drain pin and enters to the high impedance state after outputting a continuous
4-bit serial data stream. When the data-through mode is selected, SOA1 enters to the high
impedance state after outputting an 8-bit serial data stream.
SIA2, SOA2
ADPCM serial data input (SIA2) and output (SOA2) pins for Channel 2.
These pins function the same as SIA1 and SOA1.
SIA3, SOA3
ADPCM serial data input (SIA3) and output (SOA3) pins for Channel 3.
These pins function the same as SIA1 and SOA1.
SIA4, SOA4
ADPCM serial data input (SIA4) and output (SOA4) pins for Channel 4.
These pins function the same as SIA1 and SOA1.
SYXA1 - 4 , SYRA1 - 4
SYXA1, SYXA2, SYXA3, and SYXA4 are synchronous signal input pins to define ADPCM data
input and output timings for Channel 1 (SIA1, SOA1), Channel 2 (SIA2, SOA2), Channel 3 (SIA3,
SOA3), and Channel 4 (SIA4, SOA4), respectively.
Therefore, PCM data interfaces can be used at a mutually independent timing except some
timing.
Since master clocks are generated by the internal PLL using SYXA1 to SYXA4, a synchronous
signal should be input to these pins.
Note: When PCM and ADPCM data interfaces are used at a mutually independent timing, the
timing described in "Note on Usage" should not be used.
DET1, DET2, DET3, DET4
Special ADPCM input data pattern detect pins.
When detecting a 4-bit continuous "0" pattern at the ADPCM input pins Channel 1 (SIA1),
Channel 2 (SIA2), Channel 3 (SIA3), and Channel 4 (SIA4), DET (1 - 4) goes from a digital "0" to
a digital "1" state.
A digital "1" is output at the rising edge of the clock. The fourth data bit (LSB) is clocked into the
register by the bit clock (BCKA 1 - 4) and held there until the rising edge in the next time frame.
When detecting the special data pattern in the next time frame, the digital "1" on the pins DET
(1 - 4) is remains.
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