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MSM7570L-01

Multi-Function ADPCM CODEC

Oki Electric Industry 

¡ Semiconductor

MSM7570L-01/02

SAO+, SAO–

Differential analog outputs for sound output.

Control register data CR4-B5 determines the output pins (AOUT+ and AOUT- /SAO+ and SAO-

) for the voice signal and an acoustic component of the sound tone, DTMF tone, R tone, F tone,

and various types of tones at either the VFRO pin or the SAO+ and SAO- pins. The output load

conditions of these pins are the same as those of AOUT+ and AOUT-.

SG

Analog signal ground.

The output voltage of this pin is approximately 1.4 V. Put the bypass capacitors (10 µF in parallel

with 0.1 µF ceramic type) between this pin and AG to get the specified noise characteristics.

During power-down, this output voltage is 0 V. The SG voltage if necessary should be used via

a beffer.

AG

Analog ground.

DG

Digital ground.

This ground is separated from the analog signal ground pin (AG). The DG pin must be kept as

close as possible to AG on the PCB.

VDD

+3 V power supply.

PDN/RESET

Power down and reset control input.

A “0” level makes the IC enter a power down state. At the same time, all control register data are

reset to the initial state. Set this pin to “1” during normal operating mode. The power down state

is controlled by a logical OR with CR0-B5 of the control register. When using PDN/RESET for

power down and reset control, set CR0-B5 to digital “0”.

The reset width (during “L”) should be 200ns or more.

MCK

Master clock input.

The frequency must be 12.288 MHz or 19.2 MHz. The applied clock frequency is selected by the

control register data CR0-B6. The master clock signal may be asynchronous with BCLK, XSYNC,

and RSYNC.

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