MSM7662 Ver la hoja de datos (PDF) - Oki Electric Industry
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componentes Descripción
Lista de partido
MSM7662 Datasheet PDF : 62 Pages
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¡ Semiconductor
PEDL7662-02
MSM7662
PIN DESCRIPTIONS (continued)
Pin
53 to 60
61
62
63 to 70
71
72
73
74
75
76
77
78
79
80
Symbol
Y[7] to Y[0]
DVDD
DGND
C[7] to C[0]
ODD/EVEN
HVALID
VVALID
VSYNC_L
HSYNC_L
CLKXO
CLKX2O
DGND
DVDD
CLKX2
Type
Description
Data output Y[7]: MSB, Y[0]: LSB
During ITU-RBT.656 output mode: YCbCr 8-bit data output
During 8-bit (YCbCr) output mode: YCbCr 8-bit data output
O
During 16-bit (YCbCr) output mode: Y 8-bit data output
During 24-bit RGB output mode: G 8-bit data output
Output mode is set by pin 27 or 28, or register MRA [7:6].
— Digital power supply
— Digital ground
Data output C[7]: MSB, C[0]: LSB
During ITU-RBT.656 output mode: Hi-Z
During 8-bit (YCbCr) output mode: Hi-Z
O
During 16-bit (YCbCr) output mode: CbCr 8-bit data output
During 24-bit RGB output mode: R 8-bit data output
Output mode is set by pin 27 or 28, or register MRA [7:6].
Field display output
O
If field is odd, "H" is output.
Horizontal valid pixel timing output pin
O
If section is valid, "H" is output.
Vertical valid line timing output pin
O
If section is valid, "H" is output.
O Vertical sync signal (V sync) output pin
O Horizontal sync signal (H sync) output pin
Pixel clock output
During double-speed input mode (pin 42 = 0): One half of system clock
O frequency is output.
During normal input mode (pin 42 = 1): The same frequency as system
clock frequency is output.
System clock output
O
System clock input is directly output.
— Digital ground
— Digital power supply
System clock input (selected by operation mode)
Normal input mode Double-speed input mode
NTSC ITU-RBT.601 13.5 MHz
27 MHz
I NTSC Square Pixel 12.272727 MHz
24.545454 MHz
NTSC 4fsc
14.31818 MHz
28.63636 MHz
PAL ITU-RBT.601 13.5 MHz
27 MHz
PAL Square Pixel 14.75 MHz
29.5 MHz
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