MT8985(1995) Ver la hoja de datos (PDF) - Mitel Networks
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MT8985 Datasheet PDF : 18 Pages
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MT8985
STi3
STi4
STi5
STi6
STi7
VDD
F0i
C4i
A0
A1
A2
6 5 4 3 2 1 44 43 42 41 40
7
39
8
38
9
37
10
36
11
35
12
34
13
33
14
32
15
31
16
30
17
29
1819 20 21 22 23 24 25 26 27 28
STo3
STo4
STo5
STo6
STo7
VSS
D0
D1
D2
D3
D4
STi3
1
STi4
2
STi5
3
STi6
4
STi7
5
VDD
6
F0i
7
C4i
8
A0
9
A1
10
A2
11
33 STo3
32 STo4
31 STo5
30 STo6
29 STo7
28 VSS
27 D0
26 D1
25 D2
24 D3
23 D4
44 PIN PLCC
DTA 1
STi0 2
STi1 3
STi2 4
STi3 5
STi4 6
STi5 7
STi6 8
STi7 9
VDD 10
F0i 11
C4i 12
A0 13
A1 14
A2 15
A3 16
A4 17
A5 18
DS 19
R/W 20
40 CSTo
39 ODE
38 STo0
37 STo1
36 STo2
35 STo3
34 STo4
33 STo5
32 STo6
31 STo7
30 VSS
29 D0
28 D1
27 D2
26 D3
25 D4
24 D5
23 D6
22 D7
21 CS
40 PIN CERDIP/PLASTIC DIP
44 PIN QFP
Pin Description
Figure 2 - Pin Connections
Pin #
40 44 44 Name
DIP PLCC QFP
Description
1 2 40 DTA Data Acknowledgement (Open Drain Output). This active low output indicates that
a data bus transfer is complete. A pull-up resistor is required at this output.
2-9 3-5 41-43 STi0- ST-BUS Input 0 to 7 (Inputs). Serial data input streams. These streams have 32
7-11 1-5 STi7 channels at data rates of 2.048 Mbit/s.
10 12 6 VDD +5 Volt Power Supply rail.
11 13 7 F0i Frame Pulse (Input): This input accepts and automatically identifies frame
synchronization signals formatted according to different backplane specifications
such as ST-BUS and GCI.
12 14 8 C4i Clock (Input). 4.096 MHz serial clock for shifting data in and out of the data streams.
13-18 15-17 9-11 A0-A5 Address 0 to 5 (Inputs). These lines provide the address to MT8985 internal
19-21 13-15
registers.
19 22 16
DS Data Strobe (Input). This is the input for the active high data strobe on the
microprocessor interface. This input operates with CS to enable the internal read and
write generation.
20 23 17 R/W Read/Write (Input). This input controls the direction of the data bus lines (D0-D7)
during a microprocessor access.
2-46
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