MT8981D Ver la hoja de datos (PDF) - Zarlink Semiconductor Inc
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MT8981D Datasheet PDF : 20 Pages
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MT8981D
No Corresponding Memory
- These bits give 0s if read.
Per Channel
Control Bits
Data Sheet
7
6
5
4
3
2
1
0
Bit
Name
Description
2
Message When 1, the contents of the corresponding location in Connection Memory Low are output on the
Channel location’s channel and stream. When 0, the contents of the corresponding location in Connection
Memory Low act as an address for the Data Memory and so determine the source of the
connection to the location’s channel and stream.
1
Unused
0
Output If the ODE pin is high and bit 6 of the Control Register is 0, then this bit enables the output driver
Enable for the location’s channel and stream. This allows individual channels on individual streams to be
made high-impedance, allowing switching matrices to be constructed. A 1 enables the driver and a
0 disables it.
Figure 5 - Connection Memory High Bits
(unused)
Stream
Address
Bits
Channel
Address
Bits
7
6
5
4
3
2
1
0
Bit
Name
Description
7
(Unused) Must be a 0.
6-5*
Stream The number expressed in binary notation on these 2 bits is the number of the ST-BUS stream for
Address the source of the connection. Bit 6 is the most significant bit. e.g., if bit 6 is 1, and bit 5 is 0, then
Bits* the source of the connection is a channel on STi2.
4-0*
Channel The number expressed in binary notation on these 5 bits is the number of the channel which is the
Address source of the connection (The ST-BUS stream where the channel lies is defined by bits 6 and 5.).
Bits* Bit 4 is the most significant bit. e.g., if bit 4 is 1, bit 3 is 0, bit 2 is 0, bit 1 is 1 and bit 0 is 1, then
the source of the connection is channel 19.
*If bit 2 of the corresponding Connection High location is 1 or if bit 6 of the Control Register is 1, then these entire 8 bits are
output on the channel and stream associated with this location. Otherwise, the bits are used as indicated to define the source
of the connection which is output on the channel and stream associated with this location.
Figure 6 - Connection Memory Low Bits
7
Zarlink Semiconductor Inc.
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