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MT9040

T1/E1 Synchronizer

Zarlink Semiconductor Inc 

MT9040

Data Sheet

Pin Description (continued)

Pin # Name

Description

12

F0o Frame Pulse ST-BUS 2.048Mb/s (CMOS Output). This is an 8kHz 244ns active low framing

pulse, which marks the beginning of an ST-BUS frame. This is typically used for ST-BUS

operation at 2.048Mb/s and 4.096Mb/s. See Figure 11.

13

RSP Receive Sync Pulse (CMOS Output). This is an 8kHz 488ns active high framing pulse, which

marks the beginning of an ST-BUS frame. This is typically used for connection to the Siemens

MUNICH-32 device. See Figure 12.

14

TSP Transmit Sync Pulse (CMOS Output). This is an 8kHz 488ns active high framing pulse,

which marks the beginning of an ST-BUS frame. This is typically used for connection to the

Siemens MUNICH-32 device. See Figure 12.

15

F8o Frame Pulse (CMOS Output). This is an 8kHz 122ns active high framing pulse, which marks

the beginning of a frame. See Figure 11.

16 C1.5o Clock 1.544MHz (CMOS Output). This output is used in T1 applications.

18 LOCK Lock Indicator (CMOS Output). This output goes high when the PLL is frequency locked to

the input reference.

19

C2o Clock 2.048MHz (CMOS Output). This output is used for ST-BUS operation at 2.048Mb/s.

20

C4o Clock 4.096MHz (CMOS Output). This output is used for ST-BUS operation at 2.048Mb/s

and 4.096Mb/s.

21 C19o Clock 19.44MHz (CMOS Output). This output is used in OC3/STS3 applications.

22 FLOCK Fast Lock Mode (Input). Set high to allow the PLL to quickly lock to the input reference (less

than 500 ms locking time).

24

IC Internal Connection. Tie low for normal operation.

25

C8o Clock 8.192MHz (CMOS Output). This output is used for ST-BUS operation at 8.192Mb/s.

26 C16o Clock 16.384MHz (CMOS Output). This output is used for ST-BUS operation with a

16.384MHz clock.

27

C6o Clock 6.312 Mhz (CMOS Output). This output is used for DS2 applications.

29

IM Impairment Monitor (CMOS Output). A logic high on this pin indicates that the Input

Impairment Monitor has automatically put the device into Freerun Mode.

30

IC Internal Connection. Tie high for normal operation.

32

NC No Connection. Leave open circuit.

33,34,

42

IC Internal Connection. Tie low for normal operation.

36

MS Mode/Control Select (Input). This input determines the state (Normal or Freerun) of

operation. The logic level at this input is gated in by the rising edge of F8o. See Table 2.

37, 39 IC Internal Connection. Tie low for normal operation.

40

FS2 Frequency Select 2 (Input). This input, in conjunction with FS1, selects which of four possible

frequencies (8kHz, 1.544MHz, 2.048MHz or 19.44MHz) may be input to the REF input. See

Table 1.

41

FS1 Frequency Select 1 (Input). See pin description for FS2.

44

TDO Test Serial Data Out (CMOS Output). JTAG serial data is output on this pin on the falling

edge of TCK. This pin is held in high impedance state when JTAG scan is not enabled.

3

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