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MT9045

T1/E1/OC3 System Synchronizer

Zarlink Semiconductor Inc 

MT9045

Data Sheet

Description

The MT9045 T1/E1/OC3 System Synchronizer contains a digital phase-locked loop (DPLL), which provides timing

and synchronization signals for multitrunk T1 and E1 primary rate transmission links and STS-3/OC3 links.

The MT9045 generates ST-BUS clock and framing signals that are phase locked to either a 19.44 MHz, 2.048MHz,

1.544MHz, or 8kHz input reference.

The MT9045 is compliant with AT&T TR62411 and Bellcore GR-1244-CORE Stratum 3, Stratum 4 Enhanced, and

Stratum 4 and ETSI ETS 300 011; and ITU-T G.813 Option 1 for 2048 kbit/s interfaces. It will meet the jitter/wander

tolerance, jitter/wander transfer, intrinsic jitter/wander, frequency accuracy, capture range, phase change slope,

holdover frequency and MTIE requirements for these specifications.

VSS

1

48 TMS

RST 2

47 TCK

TCLR 3

46 TRST

SECOOR 4

45 TDI

SEC 5

44 TDO

PRI 6

43 PRIOOR

Vdd 7

42 IC

OSCo 8

41 FS1

OSCi 9

40 FS2

Vss 10

39 IC

F16o 11

F0o 12

SSOP

38

37

RSEL

MS1

RSP 13

TSP 14

36 MS2

35 Vdd

F8o 15

34 IC

C1.5o 16

33 IC

Vdd 17

32 NC

LOCK 18

31 Vss

C2o 19

30 PCCi

C4o 20

29 HOLDOVER

C19o 21

28 Vdd

FLOCK 22

27 C6o

Vss 23

26 C16o

IC 24

25 C8o

Figure 2 - Pin Connections

2

Zarlink Semiconductor Inc.

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