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MT9123AE

Dual Voice Echo Canceller

Mitel Networks 

MT9123

Preliminary Information

Enable Strobe Pin

Echo Canceller

Port

ENA1

A

1

ENB1

B

1

ENA2

A

2

ENB2

B

2

Table 5 - SSI Enable Strobe Pins

PCM Law and Format Control (LAW, FORMAT)

The PCM companding/coding law used by the

MT9123 is controlled through the LAW and FORMAT

pins. ITU-T G.711 companding curves for µ-Law and

A-Law are selected by the LAW pin. PCM coding

ITU-T G.711 and Sign-Magnitude are selected by the

FORMAT pin. See Table 6.

Bit Clock (BCLK/C4i)

The BCLK/C4i pin is used to clock the PCM data in

both SSI (BCLK) and ST-BUS (C4i) operations.

In SSI operation, the bit rate is determined by the

BCLK frequency. This input must contain either eight

or sixteen clock cycles within the valid enable strobe

window. BCLK may be any rate between 128 KHz to

4.096 MHz and can be discontinuous outside of the

enable strobe windows defined by ENA1, ENB1,

ENA2 and ENB2 pins. Incoming PCM data (Rin, Sin)

are sampled on the falling edge of BCLK while

outgoing PCM data (Sout, Rout) are clocked out on

the rising edge of BCLK. See Figure 17.

In ST-BUS operation, connect the system C4

(4.096MHz) clock to the C4i pin.

PCM Code

Sign-Magnitude

FORMAT=0

µ/A-LAW

LAW = 0 or 1

ITU-T (G.711)

FORMAT=1

µ-LAW

LAW = 0

A-LAW

LAW =1

+ Full Scale

1111 1111

1000 0000 1010 1010

+ Zero

1000 0000

1111 1111 1101 0101

- Zero

0000 0000

0111 1111 0101 0101

- Full Scale

0111 1111

0000 0000 0010 1010

Table 6 - Companded PCM

Linear PCM

The 16-bit 2’s complement PCM linear coding

permits a dynamic range beyond that which is

specified in ITU-T G.711 for companded PCM. The

echo-cancellation algorithm will accept 16 bits 2’s

complement linear code which gives a dynamic

range of +15dBm0.

Linear PCM data must be formatted as 14-bit, 2’s

complement data with three bits of sign extension in

the most significant positions (i.e.: S,S,S,12,11,

...1,0) for a total of 16 bits where “S” is the extended

sign bit. When A-Law is converted to 2’s complement

linear format, it must be scaled up by 6dB (i.e. left

shifted one bit) with a zero inserted into the least

significant bit position. See Figure 8.

Master Clock (MCLK)

A nominal 20MHz master clock (MCLK) is required

for execution of the MT9123 algorithms. The MCLK

input may be asynchronous with the 8KHz frame. If

only one channel operation is required, (Echo

Canceller A only) the MCLK can be as low as

9.6MHz.

Microport

The serial microport provides access to all MT9123

internal read and write registers and it is enabled

when CONFIG1 and CONFIG2 pins are both set to

logic 0. This microport is compatible with Intel MCS-

51 (mode 0), Motorola SPI (CPOL=0, CPHA=0), and

National Semiconductor Microwire specifications.

The microport consists of a transmit/receive data pin

(DATA1), a receive data pin (DATA2), a chip select

pin (CS) and a synchronous data clock pin (SCLK).

The MT9123 automatically adjusts its internal timing

and pin configuration to conform to Intel or Motorola/

National requirements. The microport dynamically

senses the state of the SCLK pin each time CS pin

becomes active (i.e. high to low transition). If SCLK

pin is high during CS activation, then Intel mode 0

timing is assumed. In this case DATA1 pin is defined

as a bi-directional (transmit/receive) serial port and

DATA2 is internally disconnected. If SCLK is low

during CS activation, then Motorola/National timing

is assumed and DATA1 is defined as the data

transmit pin while DATA2 becomes the data receive

pin. The MT9123 supports Motorola half-duplex

processor mode (CPOL=0 and CPHA=0). This

means that during a write to the MT9123, by the

Motorola processor, output data from the DATA1 pin

8-54

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