MT9123
Preliminary Information
COMMAND/ADDRESS
DATA INPUT
DATA 2
Receive
DATA 1
Transmit
R/W A5 A4 A3 A2 A1 A0 X
High Impedance
D7 D6 D5 D4 D3 D2 D1 D0
DATA OUTPUT
D7 D6 D5 D4 D3 D2 D1 D0
SCLK
CS
Delays due to internal processor timing which are transparent to the MT9123.
The MT9123: latches receive data on the rising edge of SCLK
outputs transmit data on the falling edge of SCLK
The falling edge of CS indicates that a COMMAND/ADDRESS byte will be transmitted from the microprocessor. The subsequent
byte is always data followed by CS returning high.
A new COMMAND/ADDRESS byte may be loaded only by CS cycling high then low again.
The COMMAND/ADDRESS byte contains: 1 bit - Read/Write
6 bits - Addressing Data
1 bit - Unused
Figure 11 - Serial Microport Timing for Motorola Mode 00 or National Microwire
8-60