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MT9123AP

Dual Voice Echo Canceller

Mitel Networks 

MT9123

Preliminary Information

Pin Description (continued)

Pin #

19/20

Name

S2/S1

Description

Selection of Echo Canceller A Functional States (Input).

Controllerless Mode: Selects Echo Canceller A functional states according to Table 2.

Controller Mode: S2 and S1 pins become DATA2 and DATA1 pins respectively.

19 DATA2 Serial Data Receive (Input).

In Motorola/National serial microport operation, the DATA2 pin is used for receiving data. In

Intel serial microport operation, the DATA2 pin is not used and must be tied to Vss or Vdd.

20 DATA1 Serial Data Port (Bidirectional).

In Motorola/National serial microport operation, the DATA1 pin is used for transmitting data. In

Intel serial microport operation, the DATA1 pin is used for transmitting and receiving data.

21

F0od Delayed Frame Pulse Output (Output). In ST-BUS operation, this pin generates a delayed

frame pulse after the 4th channel time slot and is used for daisy-chaining multiple ST-BUS

devices. See Figures 5 to 8.

In SSI operation, this pin outputs logic low.

22

VDD Positive Power Supply. Nominally 5 volts.

23

Sout Send PCM Signal Output (Output). 128 kbit/s to 4096 kbit/s serial PCM output stream. Data

may be in either companded or 2’s complement linear PCM format. Two PCM channels are

time-multiplexed on this pin. These are the Send Out signals after echo cancellation and Non-

linear processing. Data bits are clocked out following SSI or ST-BUS timing requirements.

24

Rout Receive PCM Signal Output (Output). 128 kbit/s to 4096 kbit/s serial PCM output stream.

Data may be in either companded or 2’s complement linear PCM format. Two PCM channels

are time-multiplexed on this pin. This output pin is provided for convenience in some

applications and may not always be required. Data bits are clocked out following SSI or ST-

BUS timing requirements.

25

F0i Frame Pulse (input). In ST-BUS operation, this is a frame alignment low going pulse. SSI

operation is enabled by connecting this pin to Vss.

26 BCLK/C4i Bit Clock/ST-BUS Clock (Input). In SSI operation, BCLK pin is a 128 kHz to 4.096 MHz bit

clock. This clock must be synchronous with ENA1, ENA2, ENB1 and ENB2 enable strobes.

In ST-BUS operation, C4i pin must be connected to the 4.096MHz (C4) system clock.

27/28 CONFIG1/ Device Configuration Pins (Inputs). When CONFIG1 and CONFIG2 pins are both logic 0,

CONFIG2 the MT9123 serial microport is enabled. This configuration is defined as Controller Mode.

When CONFIG1 and CONFIG2 pins are in any other logic combination, the MT9123 is

configured in Controllerless Mode. See Table 3.

Notes:

1. All unused inputs should be connected to logic low or high unless otherwise stated. All outputs should be left open circuit when not used.

2. All inputs have TTL compatible logic levels except for MCLK, Sin and Rin pins which have CMOS compatible logic levels and PWRDN

pin which has Schmitt trigger compatible logic levels.

3. All outputs are CMOS pins with CMOS logic levels.

8-48

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