MT90870 Ver la hoja de datos (PDF) - Zarlink Semiconductor Inc
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MT90870 Datasheet PDF : 86 Pages
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MT90870
Data Sheet
Changes Summary
The following table captures the changes from the December 2002 issue.
Page
14
21
23
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24
25
26
27
52
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54
73
Item
Change
Pin Description, C8i
The internal frame boundary alignment description
is changed from the clock rising or falling edge to
rising edge only. Also added description to specify
setting the C8IPOL bit in the Control Register to
one for clock rising edge alignment operation.
Figure 6, Local Port Timing Diagram for
2,4,8 and 16 Mb/s stream rates
Changed C8i frame boundary active edge from
falling to rising edge.
Figure 7, Backplane Port Timing Diagram Changed C8i frame boundary active edge from
for 2, 4, 8, 16 and 32 Mb/s stream rates falling to rising edge.
Section 2.3. Backplane Frame Pulse Input Removed the falling clock edge frame boundary
and Master Input Clock Timing
alignment option.
Figure 8, Backplane and Local Frame
Changed C8i frame boundary active edge from
Pulse Alignment for Data Rates of 2 Mb/s, falling to rising edge.
4 Mb/s, 8 Mb/s and 16 Mb/s
Figure 9, Backplane and Local Input
Channel Delay Timing Diagram (8 Mb/s)
Changed FPo and C8o to FPi and C8i respectively
and showing rising C8i frame boundary active
edge.
Figure 10, Backplane and Local Input Bit
Delay Timing Diagram for Data Rate of
16 Mb/s
Changed FPo and C8o to FPi and C8i respectively
and showing rising C8i frame boundary active
edge.
Figure 11, Backplane and Local Input Bit
Delay Timing Diagram for Data Rate of
8 Mb/s
Changed FPo and C8o to FPi and C8i
respectively.
Section 13.1. Control Register (CR) Bit 6,
C8IPOL
Changed description to specify Bit 6, C8IPOL
must be set high for rising clock edge frame
boundary alignment operation.
Figure 18, Frame Boundary Conditions,
ST- BUS Operation
Removed waveforms showing C8i falling edge
frame boundary option.
Figure 19, Frame Boundary Conditions,
GCI - BUS Operation
Removed waveforms showing C8i falling edge
frame boundary option.
Backplane and Local Clock Timing:
Item 2, Backplane Frame Pulse Setup
Time before C8i clock falling edge
Item 3, Backplane Frame Pulse Hold Time
from C8i clock falling edge
Item 2, Backplane Frame Pulse Setup Time
before C8i clock falling edge changed to
Backplane Frame Pulse Setup Time before C8i
clock rising edge.
Item 3, Backplane Frame Pulse Hold Time from
C8i clock falling edge changed to Backplane
Frame Pulse Hold Time from C8i clock rising
edge.
9
Zarlink Semiconductor Inc.
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