SDRAM (Rev.1.3)
Mar98
MITSUBISHI LSIs
M5M4V64S20ATP-8A,-8L,-8, -10L, -10
64M (4-BANK x 4194304-WORD x 4-BIT) Synchronous DRAM
[ BURST WRITE ]
A burst write operation is enabled by setting A9=0. A burst write starts in the same cycle as a
write command set. (The latency of data input is 0.) The burst length can be set to 1,2,4,8,
and full-page, like burst read operations.
tRCD
CLK
Command
ACT
WRITE
Address
X
DQ
DQ
DQ
DQ
DQ
Y
Q0
Q0 Q1
Q0 Q1 Q2 Q3
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9 Q10
Qm Q0 Q1
BL=1
BL=2
BL=4
BL=8
BL=FP
M5M4V64S20A : m=1023
M5M4V64S30A : m=511
M5M4V64S40A : m=255
Full Page counter rolls over
and continues to count.
[ SINGLE WRITE ]
A single write operation is enabled by setting A9=1. In a single write operation, data is only
written to the column address specified by the write command set cycle without regard to the
burst length setting. (The latency of data input is 0.)
CLK
Command
Address
DQ
ACT
tRCD
X
WRITE
Y
Q0
MITSUBISHI ELECTRIC
18