M2V64S20DTP Ver la hoja de datos (PDF) - MITSUBISHI ELECTRIC

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M2V64S20DTP

64M Synchronous DRAM

MITSUBISHI ELECTRIC  

MITSUBISHI LSIs

SDRAM (Rev.3.2)

Feb.'00

M2V64S20DTP-6,-6L,-7,-7L,-8,-8L (4-BANK x 4,194,304-WORD x 4-BIT)

M2V64S30DTP-6,-6L,-7,-7L,-8,-8L (4-BANK x 2,097,152-WORD x 8-BIT)

M2V64S40DTP-6,-6L,-7,-7L,-8,-8L (4-BANK x 1,048,576-WORD x 16-BIT)

64M Synchronous DRAM

BLOCK DIAGRAM

DQ0-7

I/O Buffer

Memory Array

4096 x512 x8

Cell Array

Bank #0

Memory Array

4096 x512 x8

Cell Array

Bank #1

Memory Array

4096 x512 x8

Cell Array

Bank #2

Memory Array

4096 x512 x8

Cell Array

Bank #3

Mode

Register

Control Circuitry

Address Buffer

Clock Buffer

Control Signal Buffer

A0-11 BA0,1

CLK CKE

/CS /RAS

/CAS

/WE

DQM

Note : This figure shows the M2V64S30DTP.

The M2V64S20DTP configration is 4096x1024x4 of cell array and DQ 0-3.

The M2V64S40DTP configration is 4096x256x16 of cell array and DQ 0-15.

Type Designation Code

M2 V 64 S 3 0 D TP -8

These rules are only applied to the Synchronous DRAM family.

Access Item

Package T ype

Process Generation

Function

Organization

Synchronous DRAM

Density

Interface

Mitsubishi DRAM

-6 : 7.5ns (PC133 3-3-3),

-7 : 10ns (PC100 2-2-2),

-8 : 10ns (PC100 3-2-2)

T P : T S O P (II)

D : 5th gen.

R eserved for Future Use

2 : x4, 3 : x8, 4 : x16

64 : 64Mbit

V : LVT T L

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