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CY7C4231-25JC Ver la hoja de datos (PDF) - Cypress Semiconductor

Número de pieza
componentes Descripción
fabricante
CY7C4231-25JC
Cypress
Cypress Semiconductor Cypress
CY7C4231-25JC Datasheet PDF : 21 Pages
First Prev 11 12 13 14 15 16 17 18 19 20
CY7C4421/4201/4211/4221
CY7C4231/4241/4251
Width Expansion Configuration
Word width may be increased simply by connecting the corre-
sponding input controls signals of multiple devices. A compos-
ite flag should be created for each of the end-point status flags
(EF and FF). The partial status flags (PAE and PAF) can be
detected from any one device. Figure 2 demonstrates a 18-bit
word width by using two CY7C42X1s. Any word width can be
attained by adding additional CY7C42X1s.
When the CY7C42X1 is in a Width Expansion Configuration,
the Read Enable (REN2) control input can be grounded (See
Figure 2). In this configuration, the Write Enable 2/Load
(WEN2/LD) pin is set to LOW at Reset so that the pin operates
as a control to load and read the programmable flag offsets.
Flag Operation
The CY7C42X1 devices provide four flag pins to indicate the
condition of the FIFO contents. Empty, Full, PAE, and PAF are
synchronous.
Full Flag
The Full Flag (FF) will go LOW when device is full. Write oper-
ations are inhibited whenever FF is LOW regardless of the
state of WEN1 and WEN2/LD. FF is synchronized to WCLK,
i.e., it is exclusively updated by each rising edge of WCLK.
Empty Flag
The Empty Flag (EF) will go LOW when the device is empty.
Read operations are inhibited whenever EF is LOW, regard-
less of the state of REN1 and REN2. EF is synchronized to
RCLK, i.e., it is exclusively updated by each rising edge of
RCLK.
RESET (RS)
DATA IN (D) 18 9
WRITE CLOCK (WCLK)
WRITE ENABLE 1 (WEN1)
WRITE ENABLE 2/LOAD
(WEN2/LD)
PROGRAMMABLE (PAF)
CY7C42X1
FULL FLAG (FF) # 1
EF
FF
FULL FLAG (FF) # 2
9
RESET (RS)
9
READ CLOCK (RCLK)
READ ENABLE 1 (REN1)
CY7C42X1
OUTPUT ENABLE (OE)
PROGRAMMABLE (PAE)
EMPTY FLAG (EF) #1
EF EMPTY FLAG (EF) #2
FF
9 DATA OUT (Q) 18
Read Enable 2 (REN2)
Read Enable 2 (REN2)
42X1–16
Figure 2. Block Diagram of 64 x 9,256 x 9,512 x 9,1024 x 9,2048 x 9,4096 x 9,8192 x 9 Synchronous FIFO
Memory Used in a Width Expansion Configuration
15

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