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MX98704 Ver la hoja de datos (PDF) - Macronix International

Número de pieza
componentes Descripción
Lista de partido
MX98704
MCNIX
Macronix International MCNIX
MX98704 Datasheet PDF : 15 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
MX98704
PIN (PLCC) PIN (PQFP) PIN NAME TYPE
25
18
Test
O
26
19
GND
I
27
20
VDD
I
28
21
GND
I
29
22
VDD
I
30
23
GND
I
31
24
OP3
O
32
25
SYMCLK O
33
26
TXEN
I
34
35-39
40
27
28-32
33
TCLKIN I
TDAT4-0 I
TSB
I
41-45
34-38
RDAT4-0 O
46
39
SDO
O
47
40
RSCLK
O
48
41
LPBKB
I
49
42
TEST
I
50
43
VDD
I
51
44
GND
I
52
45
VDD
I
DESCRIPTION
Transmit Filter.
Ground.
Power Supply. 5V
Ground.
Power Supply. 5V
Ground.
Parameter Option (GND is recommended)
Local Symbol Clock. This pin supplies the frequency reference
to the transmit logic. It is the buffered 25MHz oscillator output.
Transmit Enable. When held LOW, the TDH output is forced
LOW, and TDL output is forced HIGH so that the transmitter will
output logical 0. This TTL-level signal has an internal pullup
resistor.
Transmit Clock In. This pin is a 25Mhz optional clock input.
Transmit Data. These five inputs are 4B/5B encoded transmit
data symbols, latched by the rising edge of SYMCLK. TDAT4
is the Most Significant Bit.
Three-State. While this pin input is low, the interface output pins
are forced into the high-impedance state. Pins controlled by this
signal are PDAT4-0, SDO, BYTCLK, SYMCLK and RSCLK.
This TTL-level signal has an internal pullup resistor.
Receive Data. These 5-bit parallel data symbols from trans-
ceiver are clocked by the falling edge of RSCLK and carry the
NRZ data symbols to the controller. RDAT4 is the Most
Significant Bit.
Signal Detect Output. SDO is the SDI input Asynchronized by
RSCLK. It has the same logical sense as SDI.
Recovered Symbol Clock. This is a 25MHz clock, which is
derived from the receive clock synchronization PLL circuit. It is
synchronous to the received serial data, and is the recovered bit
clock divided-by-five.
Loopback. (Active LOW) The function is used during system
loopback test to bypass the transmission medium. This TTL-
level signal has an internal pullup resistor.
Test Mode Enable. When asserted, the PDTR is in Test mode.
For normal operation, TEST pin must be tied High. This TTL-
level signal has an internal pullup resistor.
Power Supply. 5V
Ground.
Power Supply. 5V
5

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