MX98726 Ver la hoja de datos (PDF) - Macronix International

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MX98726

SINGLE CHIP 10/100 FAST ETHERNET CONTROLLER WITH uP INTERFACE

Macronix International 

MX98726

Boundary Page Pointer Register: BP (Reg0Bh/0Ah), R/W, default=x000h

Bit

0A.7-0,

0B.3-0

Symbol

BP[11:0]

Description

Boundary Page Pointer between tx/rx buffer: page TLBP[11:0] to page BP[11:0]

is tx buffer. page BP[11:0] to RHBP[11:0] is rx buffer. BP[11:0] is mapped to

MA[19:8]. MSB bit is Reg0BH.3 bit. LSB is Reg0AH.0 bit.

TX Low Boundary Page Pointer Register: TLBP (Reg0Dh/0Ch), R/W, default=x000h

Bit

0C.7-0,

0D.3-0

Symbol

TLBP[11:0]

Description

TX Low Boundary Page Pointer : Points to the first page of transmit buffer ring.

It's a static pointer that is used by GmAC to link to the last page pointed by

boundary pointer. TLBP[11:0] MSB bit is Reg0Fh.3 bit. LSB is Reg0Ch.0 bit.

Transmit Buffer Write Page Pointer Register: TWP (Reg0Fh/0Eh), R/W, default=x000h

Bit

0E.7-0,

0F.0-3

Symbol

TWP[11:0]

Description

Transmit Buffer Write Page Pointer: TWP[11:0] are mapped to MA[19:8] in the

same bit ordering. MSB bit is Reg0Fh.3 bit. LSB is Reg0Eh.0 bit. TWP is

normally controlled by device driver. An internal Byte Counter (TWPBC) is

associated with this page register.

IO Base Page Register: IOB (Reg11h/10h), R/W, default=x000h

Bit

10.7-0,

11.3-0

Symbol

IOB[11:0]

Description

IO Base Address Register: On-chip register base address register. This

address register defines the base page address of all on-chip registers

(00h-FFh). Depending on DISMIO bit which defines this page register as an

IO Base register or a Memory base register. IOB register is mapped to

physical address [19:8] during decoding. IOB is 0000h after Reset, up can

reassign new base address by writing new page number to this register.

Transmit Buffer Read Page Pointer Register: TRP (Reg13h/12h), R/W, default=x000h

Bit

12.7-0,

13.0-3

Symbol

TRP[11:0]

Description

The Page Index of transmit buffer read pointer: Current transmit read page pointer.

MSB bit is Reg13h.3 bit. LSB is Reg12h.0 bit. TRP is controlled by GMAC only.

An internal Byte Counter (TRPBC) is associated with this page register.

P/N:PM0555

MACRONIX INTERNATIONAL CO., LTD. reserves the rignt to change product and specifications without notice.

14

REV. 0.9.8, FEB. 14, 2000

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